GXM datasheet(67/244 Pages) NSC

67 / 244 page

Revision 3.1

www.national.com

Processor Programming (Continued)

3.7.3.2

Task, Gate and Interrupt Descriptors

Besides segment descriptors there are descriptors used

in task switching, switching between tasks with different

priority and those used to control interrupt functions:

• Task State Segment Table Descriptors

• Gate Table Descriptors

• Interrupt Descriptors.

All descriptors have some things in common. They are all

eight bytes in length and have three fields (BASE, LIMIT

and TYPE). The BASE field defines the starting location

for the table or segment. The LIMIT field defines the size

and the TYPE field depends on the type of descriptor.

One of the main functions of the TYPE field is to define

the access rights to the associated segment or table.

Interrupt Descriptor Table

The Interrupt Descriptor Table is an array of 256 8-byte (4-

byte for real mode) interrupt descriptors, each of which is

used to point to an interrupt service routine. Every inter-

rupt that may occur in the system must have an associ-

ated entry in the IDT. The contents of the IDTR are

completely visible to the programmer through the use of

the SIDT instruction.

The IDT descriptor table is defined by the Interrupt

Descriptor Table Register (IDTR). Some texts refer to this

Thefollowing instructions areusedinconjunction with the

IDTR registers:

• LIDT - Load memory to IDTR

• SIDT - StoreIDTR tomemory

The IDTR is set up in REAL mode using the LIDT instruc-

tion. This is possible as the LIDT instructions is only one

of two instructions that directly load a linear address

(instead of a segment relative address) in protective

mode.

As previously shown in Table 3-20, the IDTR contains a

BASE ADDRESS field and a LIMIT field that define the

IDT tables.

3.7.4

Descriptor Bit Structure

The bit structure for application and system descriptors is

shown in Table 3-21. The explanation of the TYPE field is

shown in Table 3-23 on page 68.

Table 3-21. Application and System Segment Descriptors

31 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

8765

43210

Memory Offset +4

BASE[31:24]

LIMIT[19:16]

DPL

TYPE

BASE[23:16]

Memory Offset +0

BASE[15:0]

LIMIT[15:0]

Table 3-22. Application and System Segment Descriptors Bit Definitions

Bit

Memory

Offset

Name

Description

31:24

BASE

Segment Base Address: Three fields which collectively define the base location for the segment in

4 GB physical address space.

7:0

31:16

19:16

LIMIT

Segment Limit: Two fields that define the size of the segment based on the Segment Limit

Granularity Bit.

If G = 1: Limit value interpreted in units of 4 KB.

If G = 0: Limit value is interpreted in bytes.

15:0

Segment Limit Granularity Bit: Defines LIMIT multiplier.

If G = 1: Limit value interpreted in units of 4 KB. Segment size ranges from 1 byte to 1 MB.

If G = 0: Limit value is interpreted in bytes. Segment size ranges from 4 KB to 4 GB.

Default Length for Operands and Effective Addresses:

If D = 1: Code segment = 32-bit length for operands and effective addresses

If D = 0: Code segment = 16-bit length for operands and effective addresses

If D = 1: Data segment = Pushes, calls and pop instructions use 32-bit ESP register

If D = 0: Data segment = Stack operations use 16-bit SP register

AVL

Segment Available: This field is available for use by system software.

GXM 数据表(PDF) 67 Page - National Semiconductor (TI)

GXM 数据表(HTML) 67 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载