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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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GXM 数据表(PDF) 31 Page - National Semiconductor (TI) |
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GXM 数据表(HTML) 31 Page - National Semiconductor (TI) |
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31 / 244 page  Revision 3.1 31 www.national.com Signal Definitions (Continued) CRT_VSYNC AA3 AH2 O CRT Vertical Sync CRT Vertical Sync establishes the screen refresh rate and verti- cal retrace interval for an attached CRT. The polarity is program- mable and depends on the display mode. FP_HSYNC L2 R4 O Flat Panel Horizontal Sync Flat Panel Horizontal Sync establishes the line rate and horizon- tal retrace interval for a TFT display. Polarity is programmable and depends on the display mode. This signal is an input to the CS5530. The CS5530 re-drives this signal to the flat panel. If no flat panel is used in the system, this signal does not need to be connected. FP_VSYNC J1 P2 O Flat Panel Vertical Sync Flat Panel Vertical Sync establishes the screen refresh rate and vertical retrace interval for a TFT display. Polarity is programma- ble and depends on the display mode. This signal is an input to the CS5530. The CS5530 re-drives this signal to the flat panel. If no flat panel is used in the system, this signal does not need to be connected. ENA_DISP AD5 AM6 O Display Enable Display Enable indicates the active display portion of a scan line to the CS5530. In a CS5530-based system, this signal is required to be con- nected even if there is no TFT panel in the system. VID_RDY AD1 AK2 I Video Ready This input signal indicates that the video FIFO in the CS5530 is ready to receive more data. VID_VAL M2 S3 O Video Valid VID_VAL qualifies valid video data to the CS5530. VID_DATA[7:0] Refer to Refer to Table 2-5 O Video Data Bus When the Video Port is enabled, this bus drives Video (Y-U-V) data synchronous to the VID_CLK output. PIXEL[17:0] Refer to Table 2-3 Refer to Table 2-5 O Graphics Pixel Data Bus This bus drives graphics pixel data synchronous to the PCLK output. 2.2.4 Video Interface Signals (Continued) Signal Name BGA Pin No SPGA Pin No Type Description |
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