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Revision 3.1

Processor Programming (Continued)

Table 3-39. FPU Registers

Bit

Name

Description

FPU Tag Word Register (R/W) (Note)

15:14

TAG7

TAG7: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

13:12

TAG6

TAG6: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

11:10

TAG5

TAG5: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

9:8

TAG4

TAG4: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

7:6

TAG3

TAG3: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

5:4

TAG2

TAG2: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

3:2

TAG1

TAG1: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

1:0

TAG0

TAG0: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

FPU Status Register (R/W) (Note)

Copy of ES bit (bit 7 this register)

Condition code bit 3

13:11

Top-of-Stack: Register number that points to the current TOS.

10:8

C[2:0]

Condition code bits [2:0]

7ES

Error indicator: Set to 1 if unmasked exception detected.

6SF

Stack Full: FPU Status Register: or invalid register operation bit.

Precision error exception bit

Underflow error exception bit

Overflow error exception bit

Divide-by-zero exception bit

Denormalized-operand error exception bit

Invalid operation exception bit

FPU Mode Control Register (R/W) (Note)

15:12

RSVD

Reserved: Set to 0.

11:10

Rounding Control Bits:

00 = Round to nearest or even

01 = Round towards minus infinity

10 = Round towards plus infinity

11 = Truncate

9:8

Precision Control Bits:

00 = 24-bit mantissa

01 = Reserved

10 = 53-bit mantissa

11 = 64-bit mantissa

7:6

RSVD

Reserved: Set to 0.

Precision error exception bit

FPU Mode Control Register

Overflow error exception bit

Divide-by-zero exception bit

Denormalized-operand error exception bit

Invalid-operation exception bit

Note: R/W only through the environment at store and restore commands.

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