GXM datasheet(161/244 Pages) NSC

161 / 244 page

Revision 3.1

161

www.national.com

Integrated Functions (Continued)

Index 44h

PCI Arbitration Control 2 Register (R/W)

Default Value = 00h

7PP

Ping-Pong:

0 = Arbiter grants the processor bus per the setting of bits [2:0].

1 = Arbiter grants the processor bus ownership of the PCI bus every other arbitration cycle.

6:4

FAC

Fixed Arbitration Controls: These bits control the priority under fixed arbitration. The priority table is as

follows (priority listed highest to lowest):

000 = REQ0#, REQ1#, REQ2#

001 = REQ1#, REQ0#, REQ2#

010 = REQ0#, REQ2#,REQ1#

011 = Reserved

100 = REQ1#, REQ2#, REQ0#

101 = Reserved

110 = REQ2#, REQ1#, REQ0#

111 = REQ2#, REQ0#, REQ1#

Note: The rotation arbitration bits [2:0] must be set to 000 for full fixed arbitration. If rotation bits are not

set to 000, then hybrid arbitration will occur. If Ping-Pong is enabled (bit 7 = 1), the processor will

have priority every other arbitration. In this mode, the arbiter grants the PCI bus to a master and

ignores all other requests. When the master finishes, the processor will be guaranteed access. At

this point PCI requests will again be recognized. This will switch arbitration from CPU-to-PCI to

CPU-to-PCI, etc.

3RSVD

Reserved: Set to 0.

45h-FFh

Reserved

Table 4-40. PCI Configuration Registers (Continued)

Bit

Name

Description

GXM 数据表(PDF) 161 Page - National Semiconductor (TI)

GXM 数据表(HTML) 161 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载