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GXM 数据表(PDF) 187 Page - National Semiconductor (TI) |
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GXM 数据表(HTML) 187 Page - National Semiconductor (TI) |
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187 / 244 page ![]() Revision 3.1 187 www.national.com Electrical Specifications (Continued) Figure 7-1 SYSCLK Timing and Measurement Points Table 7-7. Clock Signals Symbol ParameterT 180 MHz (6x) (Note) 200 MHz (6x) (Note) 233 MHz (7x) (Note) 266 MHz (8x) (Note) Units Min Max Min Max Min Max Min Max t1 SYSCLK Period 33.3 30.0 30.0 30.0 ns t2 SYSCLK Period Stability ±250 ±250 ±250 ±250 ps t3 SYSCLK High Time 10 10 10 10 ns t4 SYSCLK Low Time 10 10 10 10 ns t5 SYSCLK Fall Time 0.15 2.0 0.15 2.0 0.15 2.0 0.15 2.0 ns t6 SYSCLK Rise Time 0.15 2.0 0.15 2.0 0.15 2.0 0.15 2.0 ns t7 DCLK Period 7.3 7.3 7.3 7.3 ns t8 DCLK Rise/Fall Time 3.0 3.0 3.0 3.0 ns t9 SDCLK_OUT, SDCLK[3:0] Period 14.5 19.5 13 17 11 16 10 13 ns t10 SDCLK_OUT, SDCLK[3:0] High Time 7.5 6.5 5.5 5 ns t11 SDCLK_OUT, SDCLK[3:0] Low Time 7.5 6.5 5.5 5 ns t12 SDCLK_OUT, SDCLK[3:0] Fall Time 0.15 2.0 0.15 2.0 0.15 2.0 0.15 2.0 ns t13 SDCLK_OUT, SDCLK[3:0] Rise Time 0.15 2.0 0.15 2.0 0.15 2.0 0.15 2.0 ns Note: SDCLK timings (t9-t13) assume an SDCLK that is a "divide by 3" from the internal core clock. Hence: 180 MHz (6x) = 60.0 MHz SDCLK 200 MHz (6x) = 66.7 MHz SDCLK 233 MHz (7x) = 77.7 MHz SDCLK 266 MHz (8x) = 88.7 MHz SDCLK SYSCLK 1.5V VIH (Min) VIL (Max) t3 t1 t6 t5 t4 |
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