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Instruction Set

This section summarizes the Geode GXm processor

instruction set and provides detailed information on the

instruction encodings. The instruction set is broken into

four categories:

• Processor Core Instruction Set - listed in Table 9-27 on

page 213

• FPU Instruction Set - listed in Table 9-29 on page 225

• MMX Instruction Set - listed in Table 9-31 on page 230

• National Semiconductor Extended MMX Instruction Set

- listed in Table 9-33 on page 235

These tables provide information on the instruction encod-

ing, and the instruction clock counts for each instruction.

The clock count values for these tables are based on the

following assumptions

All clock counts refer to the microprocessor core

internal clock frequency. For example, clock doubled

GXm

processor

cores

will

reference

clock

frequency that is twice the bus frequency.

The instruction has been prefetched, decoded and is

ready for execution.

Bus cycles do not require wait states.

There are no local bus HOLD requests delaying

processor access to the bus.

No exceptions are detected during instruction execu-

tion.

If an effective address is calculated, it does not use

two general register components. One register,

scaling and displacement can be used within the

clock count shown. However, if the effective address

calculation uses two general register components,

add one clock to the clock count shown.

All clock counts assume aligned 32-bit memory/ IO

operands.

If instructions access a 32-bit operand on odd

addresses, add one clock for read or write and add

two clocks for read and write.

For non-cached memory accesses, add two clocks

(clock doubled GXm processor cores) or four clocks

(clock tripled GXm processor cores), assuming zero

wait state memory accesses.

10. Locked cycles are not cacheable. Therefore, using the

LOCK prefix with an instruction adds additional clocks

as specified in item 9 above.

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