EM357-RTR datasheet(47/241 Pages) SILABS

47 / 241 page

Rev 1.3

6.5.2. 6.5.2Basic Sleep Modes

The power management state diagram in Figure 6.3 shows the basic operation of the power management

controller.

Figure 6.3. Power Management State Diagram

In normal operation an application may request one of two low power modes through program execution:



Idle Sleep is achieved by executing a WFI instruction while the SLEEPDEEP bit in the Cortex System

Control register (SCS_SCR) is clear. This puts the CPU into an idle state where execution is suspended

until an interrupt occurs. This is indicated by the state at the bottom of the diagram. Power is maintained to

the core logic of the EM35x during the Idle Sleeping state.



Deep sleep is achieved by executing a WFI instruction with the SLEEPDEEP bit in SCS_SCR set. This

triggers the state transitions around the main loop of the diagram, resulting in powering down the EM35x's

core logic, and leaving only the always-on domain powered. Wake up is triggered when one of the pre-

determined events occurs.

If a deep sleep is requested the EM35x first enters a pre-deep sleep state. This state prevents any section of the

chip from being powered off or reset until the SWJ goes idle (by clearing CSYSPWRUPREQ). This pre-deep sleep

state ensures debug operations are not interrupted.

In the deep sleep state the EM35x waits for a wake up event which will return it to the running state. In powering up

the core logic the ARM® CortexTM-M3 is put through a reset cycle and Ember software restores the stack and

application state to the point where deep sleep was invoked.

DEEP SLEEP

EMULATED

DEEP SLEEP

PRE-DEEP

SLEEP

RUNNING

IDLE SLEEP

CDBGPWRUPREQ set

CDBGPWRUPREQ cleared

Deep sleep requested

(WFI instruction with SLEEP_DEEP=1)

Interr

upt

CSY

SPW

RUP

REQ

& IN

HIB

Wak

e up

even

(rese

ts th

e pro

cess

or)

& C

Sleep requ

ested

(WFI instr

uction with

SLEEP_D

EEP=0)

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