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EM357-RTR 数据表(PDF) 44 Page - Silicon Laboratories

部件名 EM357-RTR
功能描述  High-Performance, Integrated ZigBee/802.15.4 System-on-Chip
PDF  241 Pages
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制造商  SILABS [Silicon Laboratories]
网页  http://www.silabs.com
标志 SILABS - Silicon Laboratories

EM357-RTR 数据表(HTML) 44 Page - Silicon Laboratories

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Rev 1.3
6.3.4. Low-Frequency Crystal Oscillator (OSC32K)
A low-frequency 32.768 kHz crystal oscillator (OSC32K) is provided as an optional timing reference for on-chip
timers. This oscillator is designed for use with an external watch crystal. When using the 32.768 kHz crystal, you
must connect it to GPIO PC6 and PC7 and must configure these two GPIOs for analog input. Alternatively, when
PC7 is configured as a digital input, PC7 can accept an external digital clock input instead of a 32.786 kHz crystal.
The digital clock input signal must be a 1 V peak-to-peak sine wave with a dc bias of 0.5 V. Refer to "7. GPIO
(General Purpose Input/Output)" on page 50 for GPIO configuration details. Using the low-frequency oscillator,
crystal or digital clock, is enabled through Ember software.
Table 6.9 contains the specification for the low frequency crystal oscillator.
6.3.5. Clock Switching
The EM35x has two switching mechanisms for the main system clock, providing four clock modes. Table 6.10
shows these clock modes and how they affect the internal clocks.
The register bit OSC24M_CTRL_OSC24M_SEL in the OSC24M_CTRL register switches between the high-
frequency RC oscillator (OSCHF) and the high-frequency crystal oscillator (OSC24M) as the main system clock
(SYSCLK). The peripheral clock (PCLK) is always half the frequency of SYSCLK.
The register bit CPU_CLKSEL_FIELD in the CPU_CLKSEL register switches between PCLK and SYSCLK to
produce the ARM® CortexTM-M3 CPU clock (FCLK). The default and preferred mode of operation is to run the
CPU at the higher PCLK frequency, 24 MHz, to give higher processing performance for all applications and
improved duty cycling for applications using sleep modes.
In addition to these modes, further automatic control is invoked by hardware when flash programming is enabled.
To ensure accuracy of the flash controller’s timers, the FCLK frequency is forced to 12 MHz during flash
programming and erase operations.
Table 6.9. Low-Frequency Crystal Oscillator Specification
Parameter
Test conditions
Min
Typ
Max
Unit
Frequency
32.768
kHz
Accuracy
At 25 ºC
–20
+20
ppm
Load capacitance OSC32A
27
pF
Load capacitance OSC32B
18
pF
Crystal ESR
100
kΩ
Start-up time
2
s
Current consumption
At 25 °C, VDD_PADS=3.0 V
0.5
μA
Table 6.10. System Clock Modes
OSC24M_CTRL_OSC24M_
SEL
CPU_CLKSEL_
FIELD
SYSCLK
PCLK
FCLK
Flash Program/
Erase Inactive
Flash Program/
Erase Active
0 (OSCHF)
0 (Normal CPU)
12 MHz
6 MHz
6 MHz
12 MHz
0 (OSCHF)
1 (Fast CPU)
12 MHz
6 MHz
12 MHz
12 MHz
1 (OSC24M)
0 (Normal CPU)
24 MHz
12 MHz
12 MHz
12 MHz
1 (OSC24M)
1 (Fast CPU)
24 MHz
12 MHz
24 MHz
12 MHz



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