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EM357-RTR 数据表(PDF) 91 Page - Silicon Laboratories

部件名 EM357-RTR
功能描述  High-Performance, Integrated ZigBee/802.15.4 System-on-Chip
PDF  241 Pages
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制造商  SILABS [Silicon Laboratories]
网页  http://www.silabs.com
标志 SILABS - Silicon Laboratories

EM357-RTR 数据表(HTML) 91 Page - Silicon Laboratories

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91
Rev 1.3
8.5.4. Interrupts
TWI master controller interrupts are generated on the following events:

Bus command (SC_TWISTART/SC_TWISTOP) completed (0 to 1 transition of SC_TWICMDFIN)

Character transmitted and slave device responded with NACK

Character transmitted (0 to 1 transition of SC_TWITXFIN)

Character received (0 to 1 transition of SC_TWIRXFIN)

Received and lost character while receive FIFO was full (receive overrun error)

Transmitted character while transmit FIFO was empty (transmit underrun error)
To enable CPU interrupts, set the desired interrupt bits in the second-level INT_SCxCFG register, and enable the
top-level SCx interrupt in the NVIC by writing the INT_SCx bit in the INT_CFGSET register.
8.5.5. Registers
Refer to "8.3.5. Registers" on page 79 (in “8.3. SPI—Master Mode” ) for a description of the SCx_DATA,
SCx_RATELIN, and SCx_RATEEXP registers.
Note:
Substitute “1” or “2” for “x” in the following detailed descriptions.
SC1_TWISTAT: Address: 0x4000C844 Reset: 0x0
SC2_TWISTAT: Address: 0x4000C044 Reset: 0x0
Register 8.10. SCx_TWISTAT
SC1_TWISTAT: TWI Status Register
SC2_TWISTAT: TWI Status Register
Bit
31
30
29
28
27
26
25
24
Name
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Name
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Name
0
0
0
0
SC_TWICMDFIN SC_TWIRXFIN SC_TWITXFIN SC_TWIRXNAK
Bitname
Bitfield
Access
Description
SC_TWICMDFIN
[3]
R
This bit is set when a START or STOP command completes. It clears on the next TWI
bus activity.
SC_TWIRXFIN
[2]
R
This bit is set when a byte is received. It clears on the next TWI bus activity.
SC_TWITXFIN
[1]
R
This bit is set when a byte is transmitted. It clears on the next TWI bus activity.
SC_TWIRXNAK
[0]
R
This bit is set when a NACK is received from the slave. It clears on the next TWI bus
activity.



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