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EM357-RTR 数据表(PDF) 98 Page - Silicon Laboratories |
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EM357-RTR 数据表(HTML) 98 Page - Silicon Laboratories |
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98 / 241 page  Rev 1.3 98 8.6.7. Registers Refer to "8.3.5. Registers" on page 79 (in “8.3. SPI—Master Mode” ) for a description of the SCx_DATA register. SC1_UARTSTAT: Address: 0x4000C848 Reset: 0x40 Register 8.13. SC1_UARTSTAT: UART Status Register Bit 31 30 29 28 27 26 25 24 Name 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Name 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name 0 SC_ UARTTXIDLE SC_ UARTPARERR SC_ UARTFRMERR SC_ UARTRXOVF SC_ UARTTXFREE SC_ UARTRXVAL SC_ UARTCTS Bitname Bitfield Access Description SC_UARTTXIDLE [6] R This bit is set when both the transmit FIFO and the transmit serializer are empty. SC_UARTPARERR [5] R This bit is set when the byte in the data register was received with a parity error. This bit is updated when the data register is read, and is cleared if the receive FIFO is empty. SC_UARTFRMERR [4] R This bit is set when the byte in the data register was received with a frame error. This bit is updated when the data register is read, and is cleared if the receive FIFO is empty. SC_UARTRXOVF [3] R This bit is set when the receive FIFO has been overrun. This occurs if a byte is received when the receive FIFO is full. This bit is cleared by reading the data regis- ter. SC_UARTTXFREE [2] R This bit is set when the transmit FIFO has space for at least one byte. SC_UARTRXVAL [1] R This bit is set when the receive FIFO contains at least one byte. SC_UARTCTS [0] R This bit shows the logical state (not voltage level) of the nCTS input: 0: nCTS is deasserted (pin is high, 'XOFF', RS232 negative voltage); the UART is inhibited from starting to transmit a byte. 1: nCTS is asserted (pin is low, 'XON', RS232 positive voltage); the UART may transmit. |
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