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数据搜索系统，热门电子元器件搜索 |
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EM357-RTR 数据表(PDF) 80 Page - Silicon Laboratories |
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EM357-RTR 数据表(HTML) 80 Page - Silicon Laboratories |
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80 / 241 page  Rev 1.3 80 SC1SPICFG: Address: 0x4000C858 Reset: 0x0 SC2SPICFG: Address: 0x4000C058 Reset: 0x0 Register 8.6. SCx_SPICFG SC1SPICFG: SPI Configuration Register SC2SPICFG: SPI Configuration Register Bit 31 30 29 28 27 26 25 24 Name 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Name 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name 0 0 SC_SPIRXDRV SC_SPIMST SC_SPIRPT SC_SPIORD SC_SPIPHA SC_SPIPOL Bitname Bitfield Access Description SC_SPIRXDRV [5] RW Receiver-driven mode selection bit (SPI master mode only). Clear this bit to initiate transactions when transmit data is available. Set this bit to initiate transactions when the receive buffer (FIFO or DMA) has space. SC_SPIMST [4] RW Set this bit to put the SPI in master mode, clear this bit to put the SPI in slave mode. SC_SPIRPT [3] RW This bit controls behavior when the transmit serializer must send a byte and there is no data already available in/to the serializer. The conditions for sending this “busy” token are transmit buffer underrun condition when using DMA in master or slave mode, empty FIFO in slave mode, and the busy token will always be sent as the first byte every time nSSEL is asserted while operating in slave mode. Clear this bit to send the BUSY token (0xFF) and set this bit to repeat the last byte. Changes to this bit take effect when the transmit FIFO is empty and the transmit serializer is idle. Note that when the chip comes out of reset, if SC_SPIRPT is set before any data has been trans- mitted and no data is available (in the FIFO), the “last byte” that will be transmitted after the padding byte is 0x00 due to the FIFO having been reset to 0x00. SC_SPIORD [2] RW This bit specifies the bit order in which SPI data is transmitted and received. 0: Most significant bit first. 1: Least significant bit first. SC_SPIPHA [1] RW Clock phase configuration: clear this bit to sample on the leading (first edge) and set this bit to sample on the second edge. SC_SPIPOL [0] RW Clock polarity configuration: clear this bit for a rising leading edge and set this bit for a falling leading edge. |
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