EM357-RTR datasheet(86/241 Pages) SILABS

86 / 241 page

Rev 1.3

8.4.3. Operation

When the slave select (nSSEL) signal is asserted by the master, SPI transmit data is driven to the output pin MISO,

and SPI data is received from the input pin MOSI. The nSSEL pin has to be asserted to enable the transmit

serializer to drive data to the output signal MISO. A falling edge on nSSEL resets the SPI slave shift registers.

Note:

The SPI slave controller does not tri-state the MISO signal when slave select is deasserted.

Characters transmitted and received by the SPI slave controller are buffered in the transmit and receive FIFOs that

are both four entries deep. When software writes a character to the SCx_DATA register, it is pushed onto the

transmit FIFO. Similarly, when software reads from the SCx_DATA register, the character returned is pulled from

the receive FIFO. If the transmit and receive DMA channels are used, the DMA channels also write to and read

from the transmit and receive FIFOs.

Characters received are stored in the receive FIFO. Receiving characters sets the SC_SPIRXVAL bit in the

SCx_SPISTAT register, to indicate that characters can be read from the receive FIFO. Characters received while

the receive FIFO is full are dropped, and the SC_SPIRXOVF bit in the SCx_SPISTAT register is set. The receive

FIFO hardware generates the INT_SCRXOVF interrupt, but the DMA register will not indicate the error condition

until the receive FIFO is drained. Once the DMA marks a receive error, two conditions will clear the error indication:

setting the appropriate SC_TX/RXDMARST bit in the SCx_DMACTRL register, or loading the appropriate DMA

buffer after it has unloaded.

Receiving a character causes the serial transmission of a character pulled from the transmit FIFO. When the

transmit FIFO is empty, a transmit underrun is detected (no data in transmit FIFO) and the INT_SCTXUND bit in

the INT_SCxFLAG register is set. Because no character is available for serialization, the SPI serializer retransmits

the last transmitted character or a busy token (0xFF), determined by the SC_SPIRPT bit in the SCx_SPICFG

When the transmit FIFO and the serializer are both empty, writing a character to the transmit FIFO clears the

SC_SPITXIDLE bit in the SCx_SPISTAT register. This indicates that not all characters have been transmitted. If

characters are written to the transmit FIFO until it is full, the SC_SPITXFREE bit in the SCx_SPISTAT register is

cleared. Shifting out a transmit character to the MISO pin causes the SC_SPITXFREE bit in the SCx_SPISTAT

SC_SPITXIDLE bit in the SCx_SPISTAT register is set.

The SPI slave controller must guarantee that there is time to move new transmit data from the transmit FIFO into

the hardware serializer. To provide sufficient time, the SPI slave controller inserts a byte of padding at the start of

every new string of transmit data defined by every time nSSEL is asserted. This byte is inserted as if this byte was

placed there by software. The value of the byte of padding is always 0xFF.

8.4.4. DMA

The DMA Channels "8.7. DMA Channels" on page 101 describes how to configure and use the serial receive and

transmit DMA channels.

When using the receive DMA channel and nSSEL transitions to the high (deasserted) state, the active buffer's

receive DMA count register (SCx_RXCNTA/B) is saved in the SCx_RXCNTSAVED register. SCx_RXCNTSAVED

is only written the first time nSSEL goes high after a buffer has been loaded. Subsequent rising edges set a status

bit but are otherwise ignored. The 3-bit field SC_RXSSEL in the SCx_DMASTAT register records what, if anything,

was saved to the SCx_RXCNTSAVED register, and whether or not another rising edge occurred on nSSEL.

EM357-RTR 数据表(PDF) 86 Page - Silicon Laboratories

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