EM357-RTR datasheet(52/241 Pages) SILABS

52 / 241 page

Rev 1.3

For outputs assigned to the serial controllers, the serial interface mode registers (SCx_MODE) determine how the

GPIO pins are used.

The alternate outputs of PA4 and PA5 can either provide packet trace data (PTI_EN and PTI_DATA) or

synchronous CPU trace data (TRACEDATA2 and TRACEDATA3). The selection of packet trace or CPU trace is

made through the Ember software.

If a GPIO does not have an associated peripheral in alternate output mode, its output is set to 0.

7.3. Forced Functions

For some GPIOs, the GPIO_PxCFGH/L configuration will be overridden. These functions are forced when the

EM35x is reset and remain forced until software overrides the forced functions. Table 7.3 shows the GPIOs that

have different functions forced on them regardless of the GPIO_PxCFGH/L registers.

PA7 is forced to be the regulator enable signal, REG_EN. If an external regulator is used and controlled through

REG_EN, PA7’s forced functionality must not be overridden. If an external regulator is not used, REG_EN may be

disabled and PA7 may be reclaimed as a normal GPIO. Disabling REG_EN is done by clearing the bit

GPIO_EXTREGEN in the GPIO_DBGCFG register.

PC0, PC2, PC3, and PC4 are forced to be the Serial Wire and JTAG (SWJ) Interface. When the EM35x resets,

these four GPIOs are forced to operate in JTAG mode. Switching the debug interface between JTAG mode and

Serial Wire mode can only be accomplished by the external debug tool and cannot be affected by software

executing on the EM35x. Due to the fact that Serial Wire mode can only be invoked by an external debug tool and

JTAG mode is forced when the EM35x resets, a designer must treat all four debug GPIOs as working in unison

even though the Serial Wire interface only uses one of the GPIO, PC4.

Table 7.2. Timer 2 Output Configuration Controls

Timer 2 Output

Option Register Bit

GPIO Mapping Selected by TIM2_OR Bit

TIM2C1

TIM2_OR[4]

PA0

PB1

TIM2C2

TIM2_OR[5]

PA3

PB2

TIM2C3

TIM2_OR[6]

PA1

PB3

TIM2C4

TIM2_OR[7]

PA2

PB4

Table 7.3. GPIO Forced Functions

GPIO

Forced Mode

Forced Signal

PA7

Open-drain output

REG_EN

PC0

Input with pull up

JRST

PC2

Push-pull output

JTDO

PC3

Input with pull up

JDTI

PC4*

Input with pull up

JTMS

PC4*

Bidirectional (push-pull output or floating input) controlled by debugger interface

SWDIO

*Note:

The choice of PC4’s forced signal is controlled by an external debug tool. JTMS is forced when the SWJ is in JTAG

mode, and SWDIO is forced when the SWJ is in Serial Wire mode.

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