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EM357-RTR 数据表(PDF) 58 Page - Silicon Laboratories

部件名 EM357-RTR
功能描述  High-Performance, Integrated ZigBee/802.15.4 System-on-Chip
PDF  241 Pages
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制造商  SILABS [Silicon Laboratories]
网页  http://www.silabs.com
标志 SILABS - Silicon Laboratories

EM357-RTR 数据表(HTML) 58 Page - Silicon Laboratories

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Rev 1.3
58
7.11. Registers
Note:
Substitute “A”, “B”, or “C” for “x” in the following detailed descriptions.
GPIO_PACFGL: Address: 0x4000B000 Reset: 0x4444
GPIO_PBCFGL: Address: 0x4000B400 Reset: 0x4444
GPIO_PCCFGL: Address: 0x4000B800 Reset: 0x4444
Register 7.1. GPIO_PxCFGL
GPIO_PACFGL: Port A Configuration Register (Low)
GPIO_PBCFGL: Port B Configuration Register (Low)
GPIO_PCCFGL: Port C Configuration Register (Low)
Bit
31
30
29
28
27
26
25
24
Name
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Name
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
Px3_CFG
Px2_CFG
Bit
7
6
5
4
3
2
1
0
Name
Px1_CFG
Px0_CFG
Bitname
Bitfield
Access
Description
Px3_CFG
[15:12]
RW
GPIO configuration control.
0x0: Analog, input or output (GPIO_PxIN always reads 1).
0x1: Output, push-pull (GPIO_PxOUT controls the output).
0x4: Input, floating.
0x5: Output, open-drain (GPIO_PxOUT controls the output).
0x8: Input, pulled up or down (selected by GPIO_PxOUT: 0 = pull-down,
1 = pull-up).
0x9: Alternate output, push-pull (peripheral controls the output).
0xD: Alternate output, open-drain (peripheral controls the output).
Px2_CFG
[11:8]
RW
GPIO configuration control: see Px3_CFG above.
Px1_CFG
[7:4]
RW
GPIO configuration control: see Px3_CFG above.
Px0_CFG
[3:0]
RW
GPIO configuration control: see Px3_CFG above.



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