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EM357-RTR 数据表(PDF) 89 Page - Silicon Laboratories |
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EM357-RTR 数据表(HTML) 89 Page - Silicon Laboratories |
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89 / 241 page  89 Rev 1.3 8.5.3. Constructing Frames The TWI master controller supports generating various frame segments by means of the SC_TWISTART, SC_TWISTOP, SC_TWISEND, and SC_TWIRECV bits in the SCx_TWICTRL1 registers. Table 8.9 summarizes these frames. Table 8.9. TWI Master Frame Segments SCx_TWICTRL1 Frame Segments SC_TWIxxxx* START SEND RECV STOP 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 No pending frame segment 1 — — 1 1 1 — — — 1 1 — — — 1 1 Illegal *Note: The notation “xxx” means that the corresponding column header below is inserted to form the field name. TWI re-start segment - after transmit or frame with NACK SDAout SDAoutSLAVE SCLoutSLAVE SCLout TWI start segment SDAout SDAoutSLAVE SCLoutSLAVE SCLout SCLout TX[7]TX[6] TX[5]TX[4] TX[3]TX[2] TX[1]TX[0] SDAout SDAoutSLAVE SCLoutSLAVE (N)ACK TWI transmit segment - after (re-)start frame SCLout TX[7]TX[6] TX[5]TX[4] TX[3]TX[2] TX[1]TX[0] SDAout SDAoutSLAVE SCLoutSLAVE (N)ACK TWI transmit segment – after transmit with ACK SCLout RX[7]RX[6] RX[5]RX[4] RX[3]RX[2] RX[1]RX[0] SDAout SDAoutSLAVE SCLoutSLAVE (N)ACK TWI receive segment – transmit with ACK SCLout RX[7]RX[6] RX[5]RX[4] RX[3]RX[2] RX[1]RX[0] SDAout SDAoutSLAVE SCLoutSLAVE (N)ACK TWI receive segment - after receive with ACK TWI stop segment - after frame with NACK or stop SDAout SDAoutSLAVE SCLoutSLAVE SCLout |
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