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EM357-RTR 数据表(PDF) 77 Page - Silicon Laboratories |
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EM357-RTR 数据表(HTML) 77 Page - Silicon Laboratories |
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77 / 241 page  77 Rev 1.3 8.3.3. Operation Characters transmitted and received by the SPI master controller are buffered in transmit and receive FIFOs that are both 4 entries deep. When software writes a character to the SCx_DATA register, the character is pushed onto the transmit FIFO. Similarly, when software reads from the SCx_DATA register, the character returned is pulled from the receive FIFO. If the transmit and receive DMA channels are used, they also write to and read from the transmit and receive FIFOs. When the transmit FIFO and the serializer are both empty, writing a character to the transmit FIFO clears the SC_SPITXIDLE bit in the SCx_SPISTAT register. This indicates that some characters have not yet been transmitted. If characters are written to the transmit FIFO until it is full, the SC_SPITXFREE bit in the SCx_SPISTAT register is cleared. Shifting out a character to the MOSI pin sets the SC_SPITXFREE bit in the SCx_SPISTAT register. When the transmit FIFO empties and the last character has been shifted out, the SC_SPITXIDLE bit in the SCx_SPISTAT register is set. Characters received are stored in the receive FIFO. Receiving characters sets the SC_SPIRXVAL bit in the SCx_SPISTAT register, indicating that characters can be read from the receive FIFO. Characters received while the receive FIFO is full are dropped, and the SC_SPIRXOVF bit in the SCx_SPISTAT register is set. The receive FIFO hardware generates the INT_SCRXOVF interrupt, but the DMA register will not indicate the error condition until the receive FIFO is drained. Once the DMA marks a receive error, two conditions will clear the error indication: setting the appropriate SC_TX/RXDMARST bit in the SCx_DMACTRL register, or loading the appropriate DMA buffer after it has unloaded. To receive a character, you must transmit a character. If a long stream of receive characters is expected, a long sequence of dummy transmit characters must be generated. To avoid software or transmit DMA initiating these transfers and consuming unnecessary bandwidth, the SPI serializer can be instructed to retransmit the last Table 8.4. SPI Master Mode Formats SCx_SPICFG Frame Formats SC_SPIxxx* MST ORD PHA POL 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 — — Same as above except data is sent LSB first instead of MSB first *Note: The notation xxx means that the corresponding column header below is inserted to form the field name. SCLKout MOSIout MISOin RX[7] TX[7] RX[6] TX[6] RX[5] TX[5] RX[4] TX[4] RX[3] TX[3] RX[2] TX[2] RX[1] TX[1] RX[0] TX[0] MOSIout MISOin RX[7] TX[7] RX[6] TX[6] RX[5] TX[5] RX[4] TX[4] RX[3] TX[3] RX[2] TX[2] RX[1] TX[1] RX[0] TX[0] SCLKout MOSIout MISOin RX[7] TX[7] RX[6] TX[6] RX[5] TX[5] RX[4] TX[4] RX[3] TX[3] RX[2] TX[2] RX[1] TX[1] RX[0] TX[0] SCLKout MOSIout MISOin RX[7] TX[7] RX[6] TX[6] RX[5] TX[5] RX[4] TX[4] RX[3] TX[3] RX[2] TX[2] RX[1] TX[1] RX[0] TX[0] SCLKout |
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