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EM357-RTR 数据表(PDF) 94 Page - Silicon Laboratories |
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EM357-RTR 数据表(HTML) 94 Page - Silicon Laboratories |
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94 / 241 page  Rev 1.3 94 8.6.2. Set Up and Configuration The UART baud rate clock is produced by a programmable baud generator starting from the 24 Hz clock: The integer portion of the divisor, N, is written to the SC1_UARTPER register and the fractional part, F, to the SC1_UARTFRAC register. Table 8.11 shows the values used to generate some common baud rates and their associated clock frequency error. The UART requires an internal clock that is at least eight times the baud rate clock, so the minimum allowable setting for SC1_UARTPER is 8. The UART can miss bytes when the inter-byte gap is long or there is a baud rate mismatch between receiver and transmitter. The UART may detect a parity and/or framing error on the corrupted byte, but there will not necessarily be any error detected. The UART is best operated in systems where the other side of the communication link also uses a crystal as its timing reference, and baud rates should be selected to minimize the baud rate mismatch to the crystal tolerance. Additionally, UART protocols should contain some form of error checking (for example CRC) at the packet level to detect, and retry in the event of errors. Since the probability of corruption is low, there would only be a small effect on UART throughput due to retries. Errors may occur when: Table 8.11. UART Baud Rate Divisors for Common Baud Rates Baud Rate (bits/sec) SC1_UARTPER SC1_UARTFRAC Baud Rate Error (%) 300 40000 0 0 2400 5000 0 0 4800 2500 0 0 9600 1250 0 0 19200 625 0 0 38400 312 1 0 57600 208 1 – 0.08 115200 104 0 + 0.16 230400 52 0 + 0.16 460800 26 0 + 0.16 921600 13 0 + 0.16 baud 24 MHz 2N F + -------------------- = Tgap 10 6 baud Ferror -------------------------------------- Where: Tgap= inter-byte gap in seconds baud = baud rate in bps Ferror = relative frequency error in ppm |
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