EM357-RTR datasheet(27/241 Pages) SILABS

27 / 241 page

Rev 1.3

5. ARM® Cortex™-M3 and Memory Modules

This chapter discusses the ARM® CortexTM-M3 Microprocessor, and reviews the EM35x’s flash and RAM memory

modules as well as the Memory Protection Unit (MPU).

5.1. ARM

® Cortex™-M3 Microprocessor

The EM35x integrates the ARM® CortexTM-M3 microprocessor, revision r1p1, developed by ARM Ltd., making the

EM35x a true System-on-Chip solution. The ARM® CortexTM-M3 is an advanced 32-bit modified Harvard

architecture processor that has separate internal program and data buses, but presents a unified program and data

address space to software. The word width is 32 bits for both the program and data sides. The ARM® CortexTM-M3

allows unaligned word and half-word data accesses to support efficiently-packed data structures.

The ARM® CortexTM-M3 clock speed is configurable to 6 , 12 , or 24 MHz. For normal operation 24 MHz is

preferred over 12 MHz due to improved performance for all applications and improved duty cycling for applications

using sleep modes. The 6 MHz operation can only be used when radio operations are not required since the radio

requires an accurate 12 MHz clock.

The ARM® CortexTM-M3 in the EM35x has also been enhanced to support two separate memory protection levels.

Basic protection is available without using the MPU, but normal operation uses the MPU. The MPU allows for

protecting unimplemented areas of the memory map to prevent common software bugs from interfering with

software operation. The architecture could also allow for separation of the networking stack from the application

code using a fine granularity RAM protection module. Errant writes are captured and details are reported to the

developer to assist in tracking down and fixing issues.

5.2. Embedded Memory

Figure 5.1 shows the EM351 ARM® CortexTM-M3 memory map and Figure 5.2 shows the EM357 ARM® CortexTM-

M3 memory map.

EM357-RTR 数据表(PDF) 27 Page - Silicon Laboratories