EM357-RTR datasheet(23/241 Pages) SILABS

23 / 241 page

Rev 1.3

Figure 3.1 shows a detailed block diagram of the EM35x.

Figure 3.1. EM35x Block Diagram

The EM35x radio receiver is a low-IF, super-heterodyne receiver. The architecture has been chosen to optimize co-

existence with other devices in the 2.4 GHz band (namely Wi-Fi and Bluetooth), and to minimize power

consumption. The receiver uses differential signal paths to reduce sensitivity to noise interference. Following RF

amplification, the signal is downconverted by an image-rejecting mixer, filtered, and then digitized by an ADC.

The digital section of the receiver uses a coherent demodulator to generate symbols for the hardware-based MAC.

The digital receiver also contains the analog radio calibration routines, and controls the gain within the receiver

path.

The radio transmitter uses an efficient architecture in which the data stream directly modulates the VCO frequency.

An integrated PA provides the output power. Digital logic controls TX path and output power calibration. If the

EM35x is to be used with an external PA, use the TX_ACTIVE or nTX_ACTIVE signal to control the timing of the

external switching logic.

The integrated 4.8 GHz VCO and loop filter minimize off-chip circuitry. Only a 24 MHz crystal with its loading

capacitors is required to establish the PLL local oscillator signal.

The MAC interfaces the on-chip RAM to the RX and TX baseband modules. The MAC provides hardware-based

IEEE 802.15.4-2003 packet-level filtering. It supplies an accurate symbol time base that minimizes the

synchronization effort of the Ember software and meets the protocol timing requirements. In addition, it provides

timer and synchronization assistance for the IEEE 802.15.4-2003 CSMA-CA algorithm.

The EM35x integrates hardware support for a packet trace module, which allows robust packet-based debug. This

element is a critical component of Ember Desktop, the Ember development environment, and provides advanced

network debug capability when used with the Ember Debug Adapter (ISA3).

The EM35x integrates an ARM® CortexTM-M3 microprocessor, revision r1p1. This industry-leading core provides

32-bit performance and is very power-efficient. It has excellent code density using the ARM® Thumb-2 instruction

set. The processor can be operated at 12 or 24 MHz when using the high-frequency crystal oscillator, or at 6 MHz

ADC

RF_P,N

Program

Flash

128/192 kB

Data

RAM

12 kB

HF crystal

OSC

LF crystal

OSC

General

Purpose

ADC

Serial

Wire and

JTAG

debug

Internal LF

RC-OSC

GPIO multiplexor switch

Chip

manager

1.8V

Regulator

Bias

2nd level

Interrupt

controller

RF_TX_ALT_P,N

OSCA

OSCB

PA[7:0], PB[7:0], PC[7:0]

Encryption

acclerator

Always

Powered

Domain

ARM® CortexTM-M3

CPU with NVIC

and MPU

VREG_OUT

Watchdog

PA select

LNA

DAC

MAC

Baseband

Sleep

timer

POR

nRESET

General

purpose

timers

GPIO

registers

UART/

SPI/TWI

SYNTH

Internal HF

RC-OSC

TX_ACTIVE

SWCLK,

JTCK

Calibration

ADC

Packet Trace

CPU debug

TPIU/ITM/

FPB/DWT

1.25V

Regulator

VDD_CORE

EM357-RTR 数据表(PDF) 23 Page - Silicon Laboratories

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