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EM357-RTR 数据表(PDF) 49 Page - Silicon Laboratories

部件名 EM357-RTR
功能描述  High-Performance, Integrated ZigBee/802.15.4 System-on-Chip
PDF  241 Pages
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制造商  SILABS [Silicon Laboratories]
网页  http://www.silabs.com
标志 SILABS - Silicon Laboratories

EM357-RTR 数据表(HTML) 49 Page - Silicon Laboratories

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Rev 1.3
49
6.5.5. Registers
Address: 0x40004038 Reset: 0x0
6.6. Security Accelerator
The EM35x contains a hardware AES encryption engine accessible from the ARM® CortexTM-M3. NIST-based
CCM, CCM*, CBC-MAC, and CTR modes are implemented in hardware. These modes are described in the IEEE
802.15.4-2003 specification, with the exception of CCM*, which is described in the ZigBee Security Services
Specification 1.0
.
Register 6.1. PERIPHERAL_DISABLE
Bit
31
30
29
28
27
26
25
24
Name
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Name
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Name
0
0
PERIDIS_RSVD PERIDIS_ADC PERIDIS_TIM2 PERIDIS_TIM1 PERIDIS_SC1 PERIDIS_SC2
Bitname
Bitfield
Access
Description
PERIDIS_RSVD
[5]
RW
Reserved: This bit can change during normal operation. When writing to
PERIPHERAL_DISABLE, the value of this bit must be preserved.
PERIDIS_ADC
[4]
RW
Disable the clock to the ADC peripheral.
PERIDIS_TIM2
[3]
RW
Disable the clock to the TIM2 peripheral.
PERIDIS_TIM1
[2]
RW
Disable the clock to the TIM1 peripheral.
PERIDIS_SC1
[1]
RW
Disable the clock to the SC1 peripheral.
PERIDIS_SC2
[0]
RW
Disable the clock to the SC2 peripheral.



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