EM357-RTR datasheet(87/241 Pages) SILABS

87 / 241 page

Rev 1.3

8.4.5. Interrupts

SPI slave controller second-level interrupts are generated on the following events:



Transmit FIFO empty and last character shifted out (depending on SCx_INTMODE, either the 0 to 1

transition or the high level of SC_SPITXIDLE)



Transmit FIFO changed from full to not full (depending on SCx_INTMODE, either the 0 to 1 transition or the

high level of SC_SPITXFREE)



Receive FIFO changed from empty to not empty (depending on SCx_INTMODE, either the 0 to 1 transition

or the high level of SC_SPIRXVAL)



Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B)



Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B)



Received and lost character while receive FIFO was full (receive overrun error)



Transmitted character while transmit FIFO was empty (transmit underrun error)

To enable CPU interrupts, set desired interrupt bits in the second-level INT_SCxCFG register, and also enable the

top-level SCx interrupt in the NVIC by writing the INT_SCx bit in the INT_CFGSET register.

8.4.6. Registers

Refer to Registers (in the SPI Master Mode "8.3. SPI—Master Mode" on page 76) for a description of the

SCx_DATA, SCx_SPICFG, and SCx_SPISTAT registers.

8.5. TWI—Two Wire serial Interfaces

Both EM35x serial controllers SC1 and SC2 include a Two Wire serial Interface (TWI) master controller with the

following features:



Uses only two bidirectional GPIO pins



Programmable clock frequency (up to 400 kHz)



Supports both 7-bit and 10-bit addressing



Compatible with Philips' I2C-bus slave devices

8.5.1. GPIO Usage

The TWI master controller uses just two signals:



SDA (Serial Data) - bidirectional serial data



SCL (Serial Clock) - bidirectional serial clock

Table 8.7 lists the GPIO pins used by the SC1 and SC2 TWI master controllers. Because the pins are configured

as open-drain outputs, they require external pull-up resistors.

Table 8.7. TWI Master GPIO Usage

SDA

SCL

Direction

Input / Output

GPIO Configuration

Alternate Output

(Open Drain)

Alternate Output

(Open Drain)

SC1 Pin

PB1

PB2

SC2 Pin

PA1

PA2

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