ADAU1772BCPZ-R7 datasheet(32/117 Pages) AD

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Data Sheet

ADAU1772

Rev. C | Page 31 of 116

Table 13 lists common fractional PLL parameter settings for

48 kHz sampling rates. When the PLL is used in fractional

mode, it is very important that the N/M fraction be kept in

the range of 0.1 to 0.9 to ensure correct operation of the PLL.

The PLL can output a clock in the range of 20.5 MHz to 27 MHz,

which should be taken into account when calculating PLL values

and MCLK frequencies.

CLOCK OUTPUT

The CLKOUT pin can be used as a master clock output to clock

other ICs in the system or as the clock for the digital microphone

inputs and PDM output. This clock can be generated from the

12.288 MHz master clock of the ADAU1772 by factors of 2, 1,

½, ¼, and ⅛. If PDM mode is enabled, only ½, ¼, and ⅛ settings

produce a clock signal on CLKOUT. The factor of 2 multiplier

works properly only if the input clock was previously divided by

2 using the CC_MDIV bit.

POWER SEQUENCING

AVDD and IOVDD can each be set to any voltage between 1.8 V

and 3.3 V, and DVDD can be set between 1.1 V and 1.8 V or

between 1.1 V and 1.2 V if using the on-board regulator.

On power-up, AVDD must be powered up before or at the same

time as IOVDD. IOVDD should not be powered up when power is

not applied to AVDD.

Enabling the PD pin powers down all analog and digital circuits.

Before enabling PD (that is, setting it low), be sure to mute the

outputs to avoid any pops when the IC is powered down.

PD can be tied directly to IOVDD for normal operation.

Power-Down Considerations

When powering down the ADAU1772, be sure to mute the outputs

before AVDD power is removed; otherwise, pops or clicks may

be heard. The easiest way to achieve this is to use a regulator that

has a power good (PGOOD) signal to power the ADAU1772 or

generate a power good signal using additional circuitry external

to the regulator itself. Typically, on such regulators the power good

signal changes state when the regulated voltage drops below ~90%

of its target value. This power good signal can be connected to one

of the ADAU1772 multipurpose pins and used to mute the DAC

outputs by setting the multipurpose pin functionality to mute

both DACs in Register 0x0038 to Register 0x003E. This ensures

that the outputs are muted before power is completely removed.

Table 12. Integer PLL Parameter Settings for PLL Output = 24.576 MHz

MCLK Input (MHz)

Input Divider

(X + 1)

Integer (R)

Denominator (M)

Numerator (N)

PLL_CTRL4 Settings

(Address 0x0005)

12.288

Don’t care

0x20

24.576

Don’t care

0x10

Table 13. Fractional PLL Parameter Settings for PLL Output = 24.576 MHz

MCLK

Input

(MHz)

Input

Divider

(X + 1)

PLL_CTRL[4:0] Settings

(Address 0x0005 to Address 0x0001)

Integer

(R)

Denominator

(M)

Numerator

(N)

PLL_CTRL4

(0x0005)

PLL_CTRL3

(0x0004)

PLL_CTRL2

(0x0003)

PLL_CTRL1

(0x0002)

PLL_CTRL0

(0x0001)

125

0x31

0x12

0x00

0x7D

0x00

1625

1269

0x19

0xF5

0x04

0x59

0x06

14.4

0x33

0x3E

0x00

0x4B

0x00

19.2

0x2B

0x03

0x00

0x19

0x00

1625

1269

0x1B

0xF5

0x04

0x59

0x06

1125

721

0x1B

0xD1

0x02

0x65

0x04

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