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ADAU1772BCPZ-R7 数据表(PDF) 10 Page - Analog Devices

部件名 ADAU1772BCPZ-R7
功能描述  Four ADC, Two DAC Low Power Codec
PDF  117 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAU1772BCPZ-R7 数据表(HTML) 10 Page - Analog Devices

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Data Sheet
ADAU1772
Rev. C | Page 9 of 116
TYPICAL POWER CONSUMPTION
Typical active noise cancelling (ANC) settings. Master clock = 12.288 MHz, fS = 192 kHz. On-board regulator enabled. Two analog-to-
digital converters (ADCs) with PGA enabled and two ADCs configured for line input; no input signal. Two digital-to-analog converters
(DACs) configured for differential headphone operation; DAC outputs unloaded. Both MICBIAS0 and MICBIAS1 enabled. ASRCs and
pulse density modulated (PDM) modulator disabled. Core running 26 out of 32 possible instructions. For total power consumption, add
IOVDD at 8 kHz slave current listed in Table 4.
Table 5.
Operating Voltage
Power Management Setting
Typical AVDD Power Consumption
(mA)
Typical ADC THD + N
(dB)
Typical HP Output
THD + N (dB)
AVDD = IOVDD = 3.3 V
Normal (default)
11.5
−93
−87.5
Extreme power saving
9.4
−93
−86.5
Power saving
9.8
−93
−86.5
Enhanced performance
12.65
−93
−90.5
AVDD = IOVDD = 1.8 V
Normal (default)
9.37
−86
−91
Extreme power saving
7.40
−84.5
−87
Power saving
7.78
−84.5
−87.5
Enhanced performance
10.4
−86
−94.5
DIGITAL FILTERS
Table 6.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ADC INPUT TO DAC OUTPUT PATH
Pass-Band Ripple
DC to 20 kHz, fS = 192 kHz
±0.02
dB
Group Delay
fS = 192 kHz
38
µs
SAMPLE RATE CONVERTER
Pass Band
LRCLK < 63 kHz
0
0.475 × fS
kHz
63 kHz < LRCLK <130 kHz
0
0.4286 × fS
LRCLK > 130 kHz
0
0.4286 × fS
Pass-Band Ripple
Upsampling, 96 kHz
−0.27
0.05
dB
Upsampling, 192 kHz
−0.06
0.05
dB
Downsampling, 96 kHz
0
0.07
dB
Downsampling, 192 kHz
0
0.07
dB
Input/Output Frequency Range
8
192
kHz
Dynamic Range
100
dB
Total Harmonic Distortion + Noise
−90
dB
Startup Time
15
ms
PDM MODULATOR
Dynamic Range (A-Weighted)
112
dB
Total Harmonic Distortion + Noise
−92
dB



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