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ADAU1772BCPZ-R7 数据表(PDF) 38 Page - Analog Devices |
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ADAU1772BCPZ-R7 数据表(HTML) 38 Page - Analog Devices |
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38 / 117 page  Data Sheet ADAU1772 Rev. C | Page 37 of 116 SIGNAL PROCESSING The ADAU1772 processing core is optimized for active noise cancelling (ANC) processing. The processing capabilities of the core include biquad filters, limiters, volume controls, and mixing. The core has four inputs and four outputs. The core is controlled with a 10-bit program word, with a maximum of 32 instructions per frame. INSTRUCTIONS A complete list of instructions/processing blocks along with documentation can be found in the SigmaStudio software for the ADAU1772. The processing blocks available are • Single-precision biquad/second order filters • Absolute value • Two-input addition • T connection in SigmaStudio • Limiter with/without external detector loop • Linear gain • Volume slider • Mute • DBREG level detection DATA MEMORY The ADAU1772 data path is 26 bits (5.21 format). The data memory is 32 words of 2 × 26 bits. The double length memory enables the core to double precision arithmetic with double length data and single length coefficients. PARAMETERS Parameters, such as filter coefficients, limiter settings, and volume control settings, are saved in parameter registers. Each parameter is a 32-bit number. The format of this number depends on whether it is controlling a filter or a limiter. The number formats of different parameters are shown in Table 15. When the parameter formats use less than the full 32-bit memory space, as with the limiter parameters, the data is LSB-aligned. Table 15. Parameter Number Formats Parameter Type Format Filter Coefficient (B0, B1, B2) 5.27 Filter Coefficient (A1) 2.27 (sign extended) Filter Coefficient (A2) 1.27 (sign extended) Maximum Gain 2.23 Minimum Gain 2.23 Attack Time 24.0 Decay Time 24.0 Threshold 2.23 There are two parameter banks available. Each bank can hold a full set of 160 parameters (32 filters × 5 coefficients). Users can switch between Bank A and Bank B, allowing for two sets of parameters to be saved in memory and switched on the fly while the codec is running. Bank switching can be achieved by writing to the CORE_CONTROL register (Address 0x0009) or by using the multipurpose push-button switches, but not using a combination of the two. Parameters in the active bank should not be updated while the core is running; this will likely result in noises on the outputs. Parameters are assigned to instructions in the order in which the instructions are instantiated in the code. The instruction types that use parameters are the biquad filters and limiters. Table 17 shows the addresses of each parameter in Bank A that are associated with each of the 32 instructions, and Table 18 shows the addresses of each parameter in Bank B. Table 16 shows the addresses of the LSB aligned, 10-bit program words. Table 16. Program Addresses Instruction Instruction Address 0 0x0080 1 0x0081 2 0x0082 3 0x0083 4 0x0084 5 0x0085 6 0x0086 7 0x0087 8 0x0088 9 0x0089 10 0x008A 11 0x008B 12 0x008C 13 0x008D 14 0x008E 15 0x008F 16 0x0090 17 0x0091 18 0x0092 19 0x0093 20 0x0094 21 0x0095 22 0x0096 23 0x0097 24 0x0098 25 0x0099 26 0x009A 27 0x009B 28 0x009C 29 0x009D 30 0x009E 31 0x009F |
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