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ADAU1772BCPZ-R7 数据表(PDF) 84 Page - Analog Devices

部件名 ADAU1772BCPZ-R7
功能描述  Four ADC, Two DAC Low Power Codec
PDF  117 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAU1772BCPZ-R7 数据表(HTML) 84 Page - Analog Devices

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Data Sheet
ADAU1772
Rev. C | Page 83 of 116
PGA SLEW CONTROL REGISTER
Address: 0x0027, Reset: 0x00, Name: PGA_STEP_CONTROL
If PGA slew is disabled with the SLEW_PDx controls, the SLEW_RATE parameter is ignored for that PGA block.
Table 68. Bit Descriptions for PGA_STEP_CONTROL
Bits
Bit Name
Settings
Description
Reset
Access
[5:4]
SLEW_RATE
Controls how fast the PGA is slewed when changing gain.
0x0
RW
00
21.5 ms
01
42.5 ms
10
85 ms
3
SLEW_PD3
PGA3 slew disable.
0x0
RW
0
PGA slew enabled
1
PGA slew disabled
2
SLEW_PD2
PGA2 slew disable.
0x0
RW
0
PGA slew enabled
1
PGA slew disabled
1
SLEW_PD1
PGA1 slew disable.
0x0
RW
0
PGA slew enabled
1
PGA slew disabled
0
SLEW_PD0
PGA0 slew disable.
0x0
RW
0
PGA slew enabled
1
PGA slew disabled



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