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ADAU1772BCPZ-R7 数据表(PDF) 55 Page - Analog Devices |
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ADAU1772BCPZ-R7 数据表(HTML) 55 Page - Analog Devices |
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55 / 117 page  ADAU1772 Data Sheet Rev. C | Page 54 of 116 Bits Bit Name Settings Description Reset Access 0 COREN Main clock enable. When COREN = 0, it is only possible to write to this register and the PLL control registers (PLL_CTRL0 to PLL_CTRL5). This control also enables the PLL clock. If using the PLL, do not set COREN = 1 until LOCK in Register PLL_CTRL5 is 1. Note that after COREN is enabled, writing to the parameters is disabled until setting DSP_CLK_EN in the CORE_ENABLE register. 0x0 RW 0 Main clock disabled 1 Main clock enabled PLL DENOMINATOR MSB REGISTER Address: 0x0001, Reset: 0x00, Name: PLL_CTRL0 This register should only be written when PLL_EN = 0 in Register CLK_CONTROL. Table 31. Bit Descriptions for PLL_CTRL0 Bits Bit Name Settings Description Reset Access [7:0] M_MSB PLL denominator MSB. 0x00 RW PLL DENOMINATOR LSB REGISTER Address: 0x0002, Reset: 0x00, Name: PLL_CTRL1 This register should only be written when PLL_EN = 0 in Register CLK_CONTROL. Table 32. Bit Descriptions for PLL_CTRL1 Bits Bit Name Settings Description Reset Access [7:0] M_LSB PLL denominator LSB. 0x00 RW PLL NUMERATOR MSB REGISTER Address: 0x0003, Reset: 0x00, Name: PLL_CTRL2 This register should only be written when PLL_EN = 0 in Register CLK_CONTROL. |
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