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ADAU1772BCPZ-R7 数据表(PDF) 4 Page - Analog Devices |
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ADAU1772BCPZ-R7 数据表(HTML) 4 Page - Analog Devices |
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4 / 117 page  Data Sheet ADAU1772 Rev. C | Page 3 of 116 Serial Data Output 2/Serial Data Output 3 Input Select Register .........................................................................................67 Serial Data Output 4/Serial Data Output 5 Input Select Register .........................................................................................68 Serial Data Output 6/Serial Data Output 7 Input Select Register .........................................................................................69 ADC_SDATA0/ADC_SDATA1 Channel Select Register......70 Output ASRC0/Output ASRC1 Source Register.....................71 Output ASRC2/Output ASRC3 Source Register.....................72 Input ASRC Channel Select Register........................................73 ADC0/ADC1 Control 0 Register..............................................74 ADC2/ADC3 Control 0 Register..............................................75 ADC0/ADC1 Control 1 Register..............................................76 ADC2/ADC3 Control 1 Register..............................................77 ADC0 Volume Control Register ...............................................78 ADC1 Volume Control Register ...............................................78 ADC2 Volume Control Register ...............................................79 ADC3 Volume Control Register ...............................................79 PGA Control 0 Register..............................................................80 PGA Control 1 Register..............................................................80 PGA Control 2 Register..............................................................81 PGA Control 3 Register..............................................................82 PGA Slew Control Register........................................................83 PGA 10 dB Gain Boost Register................................................84 Input and Output Capacitor Charging Register .....................85 DSP Bypass Path Register ..........................................................86 DSP Bypass Gain for PGA0 Register........................................86 DSP Bypass Gain for PGA1 Register........................................86 MIC_BIAS0_1 Control Register ...............................................87 DAC Control Register ................................................................87 DAC0 Volume Control Register................................................88 DAC1 Volume Control Register................................................88 Headphone Output Mutes Register..........................................89 Serial Port Control 0 Register....................................................90 Serial Port Control 1 Register....................................................91 TDM Output Channel Disable Register ..................................92 PDM Enable Register .................................................................93 PDM Pattern Setting Register ...................................................94 MP0 Function Setting Register .................................................94 MP1 Function Setting Register .................................................95 MP2 Function Setting Register .................................................96 MP3 Function Setting Register .................................................97 MP4 Function Setting Register .................................................98 MP5 Function Setting Register .................................................99 MP6 Function Setting Register ...............................................100 Push-Button Volume Settings Register..................................101 Push-Button Volume Control Assignment Register ............102 Debounce Modes Register.......................................................103 Headphone Line Output Select Register................................103 Decimator Power Control Register ........................................105 ASRC Interpolator and DAC Modulator Power Control Register.......................................................................................106 Analog Bias Control 0 Register...............................................106 Analog Bias Control 1 Register...............................................107 Digital Pin Pull-Up Control 0 Register..................................108 Digital Pin Pull-Up Control 1 Register..................................109 Digital Pin Pull-Down Control 0 Register ............................110 Digital Pin Pull-Down Control 1 Register ............................111 Digital Pin Drive Strength Control 0 Register ......................112 Digital Pin Drive Strength Control 1 Register ......................113 Outline Dimensions......................................................................114 Ordering Guide .........................................................................114 REVISION HISTORY 3/14—Rev. B to Rev. C Changes to Figure 60 and Figure 62 Captions ............................25 Added Figure 64, Figure 65, Figure 66, Figure 67, Figure 68, and Figure 69, Renumbered Sequentially ....................................26 Added Figure 70, and Figure 71....................................................27 12/12—Rev. A to Rev. B Changes to Figure 90 ......................................................................47 8/12—Rev. 0 to Rev. A Changes to Figure 69 ......................................................................31 7/12—Revision 0: Initial Version |
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