ADAU1772BCPZ-R7 datasheet(92/117 Pages) AD

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Data Sheet

ADAU1772

Rev. C | Page 91 of 116

SERIAL PORT CONTROL 1 REGISTER

Address: 0x0033, Reset: 0x00, Name: SAI_1

Using 16-bit serial I/O limits device performance.

Table 80. Bit Descriptions for SAI_1

Bits

Bit Name

Settings

Description

Reset

Access

TDM_TS

Select whether to tristate unused TDM channels or to actively drive these

data slots.

0x0

Unused outputs driven

Unused outputs tristated

BCLK_TDMC

Bit width in TDM mode.

0x0

24-bit data in each TDM channel

16-bit data in each TDM channel

LR_MODE

Sets LRCLK mode.

0x0

50% duty cycle clock

Pulse—LRCLK is a single BCLK cycle wide pulse

LR_POL

Sets LRCLK polarity.

0x0

50%: when LRCLK goes low and then high, pulse mode is short positive pulse

50%: when LRCLK goes high and then low, pulse mode is short negative pulse

SAI_MSB

Sets data to be input/output either MSB or LSB first.

0x0

MSB first data

LSB first data

BCLKRATE

Sets the number of bit clock cycles per data channel.

0x0

32 BCLK cycles/channel

16 BCLK cycles/channel

BCLKEDGE

Sets the bit clock edge on which data changes.

0x0

Data changes on falling edge

Data changes on rising edge

SAI_MS

Sets the serial port into master or slave mode.

0x0

LRCLK/BCLK slave

LRCLK/BCLK master

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