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ADAU1772

Data Sheet

Rev. C | Page 40 of 116

CONTROL PORT

The ADAU1772 has both a 4-wire SPI control port and a 2-wire

I2C bus control port. Each can be used to set the memories and

registers. The IC defaults to I2C mode but can be put into SPI

control mode by pulling the SS pin low three times.

The control port is capable of full read/write operation for all

addressable memories and registers. Most signal processing

parameters are controlled by writing new values to the param-

eter memories using the control port. Other functions, such as

mute and input/output mode control, are programmed through

the registers.

All addresses can be accessed in either single-address mode or

burst mode. The first byte (Byte 0) of a control port write contains

the 7-bit IC address plus the R/W bit. The next two bytes (Byte 1

and Byte 2) are the 16-bit subaddress of the memory or register

location within the ADAU1772. All subsequent bytes (starting

with Byte 3) contain the data, such as register data, program

data, or parameter data. The number of bytes per word depends

on the type of data that is being written. Table 19 shows the word

length of the ADAU1772’s different data types. The exact formats

for specific types of writes are shown in Figure 85 and Figure 86.

Table 19. Data Word Sizes

Data Type

Word Size (bytes)

Registers

Program

Parameters

If large blocks of data need to be downloaded to the ADAU1772,

the output of the core can be halted (using the CORE_RUN bit

in the core control register (Address 0x0009)), new data can be

loaded, and then the core can be restarted. This is typically done

during the booting sequence at start-up or when loading a new

program into memory.

Registers and bits shown as reserved in the register map read back

0s. When writing to these registers and bits, such as during a burst

write across a reserved register, or when writing to reserved bits

in a register with other used bits, write 0s.

The control port pins are multifunctional, depending on the

mode in which the part is operating. Table 20 details these

multiple functions.

Table 20. Control Port Pin Functions

I2C Mode

SPI Mode

SCL/SCLK

SCL—input

SCLK—input

SDA/MISO

SDA—open-collector output

MISO—output

ADDR1/MOSI

I2C Address Bit 1—input

MOSI—input

ADDR0/SS

I2C Address Bit 0—input

SS—input

BURST MODE COMMUNICATION

Burst mode addressing, in which the subaddresses are automati-

cally incremented at word boundaries, can be used for writing

large amounts of data to contiguous memory locations. This

increment happens automatically after a single-word write unless

the control port communication is stopped (that is, a stop

condition is issued for I2C, or SS is brought high for SPI). The

registers and RAMs in the ADAU1772 range in width from one

to four bytes, so the auto-increment feature knows the mapping

between subaddresses and the word length of the destination

I2C PORT

The ADAU1772 supports a 2-wire serial (I2C-compatible)

microprocessor bus driving multiple peripherals. I2C uses two

pins—serial data (SDA) and serial clock (SCL)—to carry data

between the ADAU1772 and the system I2C master controller.

In I2C mode, the ADAU1772 is always a slave on the bus, except

when the IC is self-booting. See the Self-Boot section for details

about using the ADAU1772 in self-boot mode.

Each slave device is recognized by a unique 7-bit address. The

ADAU1772 I2C address format is shown in Table 21. The LSB of

this first byte sent from the I2C master sets either a read or write

operation. Logic Level 1 corresponds to a read operation, and

Logic Level 0 corresponds to a write operation.

Pin ADDR0 and Pin ADDR1 set the LSBs of the I2C address

(Table 22); therefore, each ADAU1772 can be set to one of four

unique addresses. This allows multiple ICs to exist on the same

I2C bus without address contention. The 7-bit I2C addresses are

shown in Table 22.

An I2C data transfer is always terminated by a stop condition.

Both SDA and SCL should have 2.0 kΩ pull-up resistors on the

lines connected to them. The voltage on these signal lines should

not be higher than IOVDD.

Table 21. I2C Address Format

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADDR1

ADDR0

Table 22. I2C Addresses

ADDR1

ADDR0

Slave Address

0x3C

0x3D

0x3E

0x3F

Addressing

Initially, each device on the I2C bus is in an idle state and

monitoring the SDA and SCL lines for a start condition and

the proper address. The I2C master initiates a data transfer by

establishing a start condition, defined by a high-to-low transition

on SDA while SCL remains high. This indicates that an address/

data stream follows. All devices on the bus respond to the start

condition and shift the next eight bits (the 7-bit address plus the

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