ADAU1772BCPZ-R7 datasheet(51/117 Pages) AD

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ADAU1772

Data Sheet

Rev. C | Page 50 of 116

APPLICATIONS INFORMATION

POWER SUPPLY BYPASS CAPACITORS

Each analog and digital power supply pin should be bypassed to

its nearest appropriate ground pin with a single 0.1 μF capacitor.

The connections to each side of the capacitor should be as short

as possible, and the trace should be routed on a single layer with no

vias. For maximum effectiveness, locate the capacitor equidistant

from the power and ground pins or slightly closer to the power pin

if equidistant placement is not possible. Thermal connections to

the ground planes should be made on the far side of the capacitor.

Each supply signal on the board should also be bypassed with a

single bulk capacitor (10 μF to 47 μF).

Figure 102. Recommended Power Supply Bypass Capacitor Layout

LAYOUT

Pin 24 is the AVDD supply for the headphone amplifiers. If the

headphone amplifiers are enabled, the PCB trace to this pin should

be wider than traces to other pins to increase the current carrying

capacity. A wider trace should also be used for the headphone

output lines.

GROUNDING

A single ground plane should be used in the application layout.

Components in an analog signal path should be placed away

from digital signals.

EXPOSED PAD PCB DESIGN

The ADAU1772 has an exposed pad on the underside of the

LFCSP. This pad is used to couple the package to the PCB for

heat dissipation. When designing a board for the ADAU1772,

special consideration should be given to the following:

•

A copper layer equal in size to the exposed pad should be

on all layers of the board, from top to bottom, and should

connect somewhere to a dedicated copper board layer (see

Figure 103).

•

Vias should be placed to connect all layers of copper,

allowing for efficient heat and energy conductivity. For an

example, see Figure 104, which has nine vias arranged in a

3 × 3 grid in the pad area.

Figure 103. Exposed Pad Layout Example, Side View (Not to Scale)

Figure 104. Exposed Pad Layout Example, Top View (Not to Scale)

VDD

GND

TO GND

TO VDD

CAPACITOR

TOP

POWER

GROUND

BOTTOM

COPPER SQUARES

VIAS

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