ADAU1772BCPZ-R7 datasheet(42/117 Pages) AD

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Data Sheet

ADAU1772

Rev. C | Page 41 of 116

R/W bit) MSB first. The device that recognizes the transmitted

address responds by pulling the data line low during the ninth

clock pulse. This ninth bit is known as an acknowledge bit. All

other devices withdraw from the bus at this point and return to

the idle condition. The R/W bit determines the direction of the

data. A Logic 0 on the LSB of the first byte indicates that the master

will write information to the peripheral, whereas a Logic 1 indicates

that the master will read information from the peripheral after

writing the subaddress and repeating the start address. A data

transfer takes place until a stop condition is encountered. A stop

condition occurs when SDA transitions from low to high while

SCL is held high. Figure 83 shows the timing of an I2C write,

and Figure 84 shows an I2C read.

Stop and start conditions can be detected at any stage during the

data transfer. If these conditions are asserted out of sequence with

normal read and write operations, the ADAU1772 immediately

jumps to the idle condition. During a given SCL high period,

the user should only issue one start condition, one stop condition,

or a single stop condition followed by a single start condition. If

an invalid subaddress is issued by the user, the ADAU1772 does

not issue an acknowledge and returns to the idle condition. If

the user exceeds the highest subaddress while in auto-increment

mode, one of two actions is taken. In read mode, the ADAU1772

outputs the highest subaddress register contents until the master

device issues a no acknowledge, indicating the end of a read. A

no-acknowledge condition is where the SDA line is not pulled

low on the ninth clock pulse on SCL. If the highest subaddress

location is reached while in write mode, the data for the invalid

byte is not loaded into any subaddress register, a no acknowledge

is issued by the ADAU1772, and the part returns to the idle

condition.

Figure 83. I2C Write to ADAU1772 Clocking

Figure 84. I2C Read from ADAU1772 Clocking

R/W

SCL

SDA

(CONTINUED)

SCL

(CONTINUED)

ADDR0

ADDR1

START BY

MASTER

FRAME 1

CHIP ADDRESS BYTE

FRAME 2

SUBADDRESS BYTE 1

FRAME 3

SUBADDRESS BYTE 2

FRAME 4

DATA BYTE 1

ACKNOWLEDGE

BY ADAU1772

ACKNOWLEDGE

BY ADAU1772

ACKNOWLEDGE

BY ADAU1772

ACKNOWLEDGE

BY ADAU1772

STOP BY

MASTER

R/W

SCL

SDA

(CONTINUED)

SCL

(CONTINUED)

SDA

(CONTINUED)

SCL

(CONTINUED)

START BY

MASTER

FRAME 2

SUBADDRESS BYTE 1

FRAME 3

SUBADDRESS BYTE 2

FRAME 4

CHIP ADDRESS BYTE

FRAME 1

CHIP ADDRESS BYTE

FRAME 5

READ DATA BYTE 1

FRAME 6

READ DATA BYTE 2

ACKNOWLEDGE

BY ADAU1772

ACKNOWLEDGE

BY ADAU1772

ACKNOWLEDGE

BY ADAU1772

ACKNOWLEDGE

BY ADAU1772

ACKNOWLEDGE

BY ADAU1772

STOP BY

MASTER

ACKNOWLEDGE

BY ADAU1772

REPEATED

START BY MASTER

R/W

ADDR0

ADDR1

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