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ADAU1772BCPZ-R7 数据表(PDF) 78 Page - Analog Devices |
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ADAU1772BCPZ-R7 数据表(HTML) 78 Page - Analog Devices |
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78 / 117 page  Data Sheet ADAU1772 Rev. C | Page 77 of 116 ADC2/ADC3 CONTROL 1 REGISTER Address: 0x001E, Reset: 0x00, Name: ADC_CONTROL3 Table 59. Bit Descriptions for ADC_CONTROL3 Bits Bit Name Settings Description Reset Access [6:5] HP_2_3_EN High-pass filter settings. 0x0 RW 00 Off 01 1 Hz 10 4 Hz 11 8 Hz 4 DMIC_POL1 Microphone polarity. 0x0 RW 0 0 positive, 1 negative 1 1 positive, 0 negative 3 DMIC_SW1 Digital microphone swap. 0x0 RW 0 Channel swap off (left channel on rising edge, right channel on falling edge) 1 Swap left and right 2 DCM_2_3 Sets the input source to ADCs or digital microphones. 0x0 RW 0 Decimator source set to ADC 1 Decimator source set to digital microphone 1 ADC_3_EN Enable ADC3. This bit must be set in conjunction with the SINC_3_EN bit in the DECIM_PWR_MODES register to fully enable or disable the ADC. 0x0 RW 0 Disable 1 Enable 0 ADC_2_EN Enable ADC2. This bit must be set in conjunction with the SINC_2_EN bit in the DECIM_PWR_MODES register to fully enable or disable the ADC. 0x0 RW 0 Disable 1 Enable |
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