ADAU1772BCPZ-R7 datasheet(59/117 Pages) AD

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ADAU1772

Data Sheet

Rev. C | Page 58 of 116

CORE CONTROL REGISTER

Address: 0x0009, Reset: 0x04, Name: CORE_CONTROL

Table 39. Bit Descriptions for CORE_CONTROL

Bits

Bit Name

Settings

Description

Reset

Access

ZERO_STATE

Zeroes the state of the data memory during bank switching. When

switching active parameter banks between two settings, zeroing the state

of the bank prevents the new filter settings from being active on old data

that is recirculating in filters. Zeroing the state may prevent filter

instability or unwanted noises upon bank switching.

0x0

Do not zero state during bank switch

Zero state during back switch

[6:5]

BANK_SL

Selects active filter bank.

0x0

Bank A active

Bank B active

Reserved

[2:1]

CORE_FS

This bit sets the core sample rate. This setting should not be changed

while the core is running. CORE_RUN must be set to 0 for this setting to be

updated.

Reserved

96 kHz

192 kHz

Reserved

CORE_RUN

Run bit for the core. This bit should only be enabled when the program

and parameters are loaded and the sample rate settings have been set.

CORE_RUN starts and stops the core at the beginning of the program.

0x0

Core off

Core on

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