ZUSBOPTSC01ZAC datasheet(228/402 Pages) ZILOG

228 / 402 page

Analog-to-Digital Converter

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

206

Sample Settling Time Register

The Sample Settling Time Register, shown in Table 108, is used to program the length of

time from the SAMPLE/HOLD signal to the START signal, when the conversion can

begin. The number of clock cycles required for settling will vary from system to system

depending on the system clock period used. The system designer should program this reg-

ister to contain the number of clocks required to meet a 0.5 µs minimum settling time.

Sample Time Register

The Sample Time Register, shown in Table 109, is used to program the length of active

time for the sample after a conversion has begun by setting the START bit in the ADC

Control Register or initiated by the PWM. The number of system clock cycles required for

sample time varies from system to system, depending on the clock period used. The sys-

tem designer should program this register to contain the number of system clocks required

to meet a 1µs minimum sample time.

Table 108. Sample and Settling Time (ADCSST)

BITS

FIELD

Reserved

SST

RESET

R/W

ADDR

F74H

Bit

Position

Value

(H)

Description

[7:5]

Reserved - Must be 0.

[4:0]

SST

0H - FH

Sample settling time in number of system clock periods to meet 0.5

µS minimum.

ZUSBOPTSC01ZAC 数据表(PDF) 228 Page - Zilog, Inc.

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