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ZUSBOPTSC01ZAC 数据表(PDF) 230 Page - Zilog, Inc. |
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ZUSBOPTSC01ZAC 数据表(HTML) 230 Page - Zilog, Inc. |
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230 / 402 page ![]() Analog-to-Digital Converter P R E L I M I N A R Y PS024604-1005 Z8 Encore!® Motor Control Flash MCUs Product Specification 208 ADC Timer Capture High Byte Register The high byte of the ADC Timer Capture Register, shown in Table 111, contains the upper eight bits of the ADC Timer 0 count. Access to the ADC Timer Capture High Byte Regis- ter is Read-Only. ADC Timer Capture Low Byte Register The low byte of the ADC Timer Capture Register, shown in Table 112, contains the lower eight bits of the ADC Timer 0 count. Access to the ADC Timer Capture Low Byte Regis- ter is Read-Only. [1] DIV4 0 DIV4 Clock is not divided 1 System Clock is divided by 4 for ADC Clock [2] DIV8 0 DIV8 Clock is not divided 1 System Clock is divided by 8 for ADC Clock [3] DIV16 0 DIV16 Clock is not divided 1 System Clock is divided by 16 for ADC Clock [7:4] 0H Reserved - must be 0. Table 111. ADC Timer Capture High Byte Register (ADCTCAP_H) BITS 7 6 5 4 3 2 1 0 FIELD ADCTCAPH RESET X R/W R ADDR F08H Bit Position Value (H) Description [7:0] 00H–FFH ADC Timer Capture Count High Byte The timer count is held in the data registers until the next ADC conversion is started. |
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