Z8F021ASH020SC datasheet(131/276 Pages) ZILOG

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PS022815-0206

Infrared Encoder/Decoder

Z8 Encore! XP® 4K Series

Product Specification

112

minus four baud rate clocks to plus eight baud rate clocks around the expected time of an

incoming pulse. If an incoming pulse is detected inside this window this process is

repeated. If the incoming data is a logical 1 (no pulse), the Endec returns to the initial state

and waits for the next falling edge. As each falling edge is detected, the Endec clock

counter is reset, resynchronizing the Endec to the incoming signal, allowing the Endec to

tolerate jitter and baud rate errors in the incoming datastream. Resynchronizing the Endec

does not alter the operation of the UART, which ultimately receives the data. The UART is

only synchronized to the incoming data stream when a Start bit is received.

Infrared Encoder/Decoder Control Register Definitions

All Infrared Endec configuration and status information is set by the UART control regis-

ters as defined beginning on page 89.

To prevent spurious signals during IrDA data transmission, set the IREN bit in the

UART Control 1 register to 1 to enable the Infrared Encoder/Decoder before enabling

the GPIO Port alternate function for the corresponding pin.

Caution:

Z8F021ASH020SC 数据表(PDF) 131 Page - Zilog, Inc.