Z8F021ASH020SC datasheet(146/276 Pages) ZILOG

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PS022815-0206

Analog-to-Digital Converter

Z8 Encore! XP® 4K Series

Product Specification

127

010 = Reserved

011 = Reserved

100 = Differential, unbuffered input

101 = Differential, buffered input with unity gain

110 = Reserved

111 = Reserved

ADC Data High Byte Register

The ADC Data High Byte (ADCD_H) register contains the upper eight bits of the ADC

output. The output is an 13-bit two’s complement value. During a single-shot conversion,

this value is invalid. Access to the ADC Data High Byte register is read-only. Reading the

ADC Data High Byte register latches data in the ADC Low Bits register.

ADCDH—ADC Data High Byte

This byte contains the upper eight bits of the ADC output. These bits are not valid during a

single-shot conversion. During a continuous conversion, the most recent conversion out-

put is held in this register. These bits are undefined after a Reset.

ADC Data Low Bits Register

The ADC Data Low Byte (ADCD_L) register contains the lower bits of the ADC output

as well as an overflow status bit. The output is a 13-bit two’s complement value. During a

single-shot conversion, this value is invalid. Access to the ADC Data Low Byte register is

read-only. Reading the ADC Data High Byte register latches data in the ADC Low Bits

Table 74. ADC Data High Byte Register (ADCD_H)

BITS

FIELD

ADCDH

RESET

XXX

R/W

RRR

ADDR

F72H

Table 75. ADC Data Low Bits Register (ADCD_L)

BITS

FIELD

ADCDL

Reserved

OVF

RESET

XXX

R/W

RRR

ADDR

F73H

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