Z8F021ASH020SC datasheet(170/276 Pages) ZILOG

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PS022815-0206

Flash Option Bits

Z8 Encore! XP® 4K Series

Product Specification

151

Trim Bit Data Register

The Trim Bid Data (TRMDR) register contains the read or write data for access to the trim

option bits.

Flash Option Bit Address Space

The first two bytes of Flash program memory at addresses 0000H and 0001H are reserved

for the user-programmable Flash option bits.

Flash Program Memory Address 0000H

WDT_RES—Watch-Dog Timer Reset

0 = Watch-Dog Timer time-out generates an interrupt request. Interrupts must be globally

enabled for the eZ8 CPU to acknowledge the interrupt request.

1 = Watch-Dog Timer time-out causes a system reset. This setting is the default for unpro-

grammed (erased) Flash.

WDT_AO—Watch-Dog Timer Always On

0 = Watch-Dog Timer is automatically enabled upon application of system power. Watch-

Dog Timer can not be disabled.

1 = Watch-Dog Timer is enabled upon execution of the WDT instruction. Once enabled,

the Watch-Dog Timer can only be disabled by a Reset or STOP Mode Recovery. This set-

ting is the default for unprogrammed (erased) Flash.

Table 88. Trim Bit Data Register (TRMDR)

BITS

FIELD

TRMDR - Trim Bit Data

RESET

000

R/W

R/WR/W

ADDR

FF7H

Table 89. Flash Option Bits at Program Memory Address 0000H

BITS

FIELD

WDT_RES WDT_AO

OSC_SEL[1:0]

VBO_AO

FRP

Reserved

FWP

RESET

UUU

R/W

R/WR/W

ADDR

Program Memory 0000H

Note: U = Unchanged by Reset. R/W = Read/Write.

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