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Z8F021ASH020SC 数据表(PDF) 175 Page - Zilog, Inc. |
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Z8F021ASH020SC 数据表(HTML) 175 Page - Zilog, Inc. |
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175 / 276 page ![]() PS022815-0206 Flash Option Bits Z8 Encore! XP® 4K Series Product Specification 156 ADC_CAL—Analog to Digital Converter Calibration Values Contains factory calibrated values for ADC gain and offset compensation. Each of the ten supported modes has one byte of offset calibration and two bytes of gain calibration. These values are read by user software to compensate ADC measurements as detailed in Software Compensation Procedure Using Factory Calibration Data on page 119. The loca- tion of each calibration byte is provided in Table 97. Table 97. ADC Calibration Data Location Info Page Address Memory Address Compensation Usage ADC Mode Reference Type 60 FE60 Offset Single-Ended Unbuffered Internal 2.0V 08 FE08 Gain High Byte Single-Ended Unbuffered Internal 2.0V 09 FE09 Gain Low Byte Single-Ended Unbuffered Internal 2.0V 63 FE63 Offset Single-Ended Unbuffered Internal 1.0V 0A FE0A Gain High Byte Single-Ended Unbuffered Internal 1.0V 0B FE0B Gain Low Byte Single-Ended Unbuffered Internal 1.0V 66 FE66 Offset Single-Ended Unbuffered External 2.0V 0C FE0C Gain High Byte Single-Ended Unbuffered External 2.0V 0D FE0D Gain Low Byte Single-Ended Unbuffered External 2.0V 69 FE69 Offset Single Ended 1x Buffered Internal 2.0V 0E FE0E Gain High Byte Single Ended 1x Buffered Internal 2.0V 0F FE0F Gain Low Byte Single Ended 1x Buffered Internal 2.0V 6C FE6C Offset Single Ended 1x Buffered External 2.0V 10 FE10 Gain High Byte Single Ended 1x Buffered External 2.0V 11 FE11 Gain Low Byte Single Ended 1x Buffered External 2.0V 6F FE6F Offset Differential Unbuffered Internal 2.0V 12 FE12 Positive Gain High Byte Differential Unbuffered Internal 2.0V 13 FE13 Positive Gain Low Byte Differential Unbuffered Internal 2.0V 30 FE30 Negative Gain High Byte Differential Unbuffered Internal 2.0V 31 FE31 Negative Gain Low Byte Differential Unbuffered Internal 2.0V 72 FE72 Offset Differential Unbuffered Internal 1.0V |
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