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ST10F280 数据表(PDF) 105 Page - STMicroelectronics |
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ST10F280 数据表(HTML) 105 Page - STMicroelectronics |
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105 / 186 page ![]() ST10F280 105/186 13 - A/D CONVERTER 13.1 - A/D Converter Module A 10-bit A/D converter with 2 x 16 multiplexed input channels and a sample and hold circuit is integrated on-chip. This A/D Converter does not have the self-calibration feature. Thus, guaran- teed Total Unadjusted Error is + 2 LSB. Refer to Section 20.3.1 - A/D Converter Characteristics for detailled characteristics. The sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the exter- nal circuitry. Convertion time is fully equivalent to the one of previous generation A/D self-calibrated Converter. To remove high frequency components from the analog input signal, a low-pass filter must be con- nected at the ADC input. Overrun error detection/protection is controlled by the ADDAT register. Either an interrupt request is generated when the result of a previous conver- sion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended until the previous result has been read. For applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the ST10F280 supports four different conversion modes: Single channel conversion mode the analog level on a specified channel is sampled once and converted to a digital result. Single channel continuous mode the analog level on a specified channel is repeatedly sampled and converted without software intervention. Auto scan mode the analog levels on a pre-spec- ified number of channels are sequentially sampled and converted. Auto scan continuous mode the number of pre-specified channels is repeatedly sampled and converted. Channel Injection Mode injects a channel into a running sequence without disturbing this sequence. The peripheral event controller stores the conversion results in memory without entering and exiting interrupt routines for each data transfer. |
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