ST10F280 datasheet(108/186 Pages) STMICROELECTRONICS

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ST10F280

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13.3.2 - Register Description

13.3.2.1 - TCR : Timer Control Register

XTCR (C000h)

Reset Value: 0000h

9876543210

000000

TFP[3:0]

TCM

TIE

TCS

TLE

TUD

TEN

RRRRRR

Bit

Function

TEN

Timer Enable

When TEN = ’0’, the Timer is disabled (reset value). To avoid glitches, it is recommended to modify TCR in

2 steps, first with new values and and second by setting TEN.

TUD

Timer Up / Down Counting

When TUD = ’0’, the Timer is counting "down" (reset value), ie the TCVR (’current value’) register content

is decremented.

When TUD = ’1’, the Timer is counting "up", ie the TCVR (’current value’) register content is incremented.

TLE

Timer Load Enable

When the counter has reached its end value (TCVR = TEVR), TCVR is (re)loaded with TSVR (’start value’)

bit.

TCS

Timer Continue / Stop

When TLE = ’0’ (no load) and when the counter has reached its end value (TCVR = TEVR), the TCVR

content continues to increment / decrement according to TUD bit when TCS = ’1’ (continue mode).

When TCS = ’0’ (stop mode reset value), TCVR is stopped and its content is frozen.

TIE

Timer Output Enable

When the counter has reached its end value (TCVR = TEVR), the XADCINJ output is set when TIE = ’1’.

When TIE = ’0’ (reset value), XADCINJ output is disabled (= ’0’).

TCM

Timer Clock Mode Must be Cleared

TCM = ’0’ (reset value), the TCVR clock is derived from internal XCLK clock according to TFP bits.

TFP[3:0]

Timer Frequency Prescaler

When TCM = ’0’ (internal clock), the TCVR register clock is derived from the XCLK clock input by dividing

XCLK by 2**(2+ TFP). The coding is as follows :

- 0000 : prescaler by 2 (reset value), XCLK divided by 4

- 0001 : prescaler by 4, XCLK divided by 8

- 0010 : prescaler by 8, XCLK divided by 16

- ...

- 1111 : prescaler by 2**16, XCLK divided by 2**17

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