ST10F280 datasheet(110/186 Pages) STMICROELECTRONICS

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ST10F280

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13.3.3 - Block Diagram

13.3.3.1 - Clocks

The XTCVR register clock is the prescaler output.

The prescaler allows to divide the basic register

frequency in order to offer a wide range of count-

ing period, from 2**2 to 2**33 cycles (note that 1

cycle = 1 XCLK periods).

13.3.3.2 - Registers

The XTCVR register input is linked to several

sources:

– XTSVR register (start value) for reload when the

period is finished, or for load when the timer is

starting.

– Incrementer output when the ’up’ mode is selected,

– Decrementer output when the ’down’ mode is

selected.

– The selection between the sources is made

through the XTCR control register.

When starting the timer, by setting TEN bit of TCR

to ’1’, XTCVR will be loaded with XTSVR value on

the first rising edge of the counting clock. That’s to

say that for counting from 0000h to 0009h for

example, 10 counting clock rising edges are

required.

The XTCVR register output is continuously com-

pared to the XTEVR register to detect the end of

the counting period. When the registers are equal,

several actions are made depending on the XTCR

control register content :

– The output XADCINJ is conditionally generated,

– XTCVR is loaded with XTSVR or stops or contin-

ues to count (see Table 22).

XTEVR, XTSVR and all TCR bits except TEN

must not be modified while the timer is counting,

ie while TEN bit of TCR = ’1’. The timer behaviour

is not guaranteed if this rule is not respected. It

implies that the timer can be configured only when

stopped (TEN = ’0’). When programming the

timer, XTEVR, XTSVR and XTCR bits except TEN

can be modified, with TEN = ’0’; then the timer is

started by modifying only TEN bit of TCR. To stop

the timer, only TEN bit should be modified, from ’1’

to ’0’.

Figure 53 : XTIMER Block Diagram

XTCR

XTSVR

XTCVR

Prescaling

XTEVR

ctl

diff

XCLK

- 1

+ 1

Timer output

DATA

(XADCINJ)

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