ST10F280 datasheet(118/186 Pages) STMICROELECTRONICS

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ST10F280

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15 - CAN MODULES

The two integrated CAN modules (CAN1 and

CAN2) are identical and handle the completely

autonomous transmission and reception of CAN

frames in accordance with the CAN specification

V2.0 part B (active) i.e. the on-chip CAN module

can receive and transmit standard frames with

11-bit identifiers as well as extended frames with

29-bit identifiers.

Because of duplication of CAN controllers, the fol-

lowing adjustements are to be considered:

– The same internal register addresses both CAN

controllers, but with the base addresses differing

in address bit A8 and separate chip select for

each CAN module. For address mapping, see

Chapter 4.

– The CAN1 transmit line (CAN1_TxD) is the alter-

nate function of the port P4.6 and the receive

line (CAN1_RxD) is P4.5.

– The CAN2 transmit line (CAN2_TxD) is the alter-

nate function of the port P4.7 and the receive

line (CAN2_RxD) is the alternate function of the

port P4.4.

– Interrupt of CAN2 is connected to the XBUS in-

terrupt line XP1 (CAN1 is on XP0).

– Because of the new XPERCON register, both

CAN modules have to be selected, before the bit

XPEN is set in SYSCON register.

– After reset, the CAN1 is selected with the related

control bit in the XPERCON register. The CAN2

is not selected.

15.1 - Memory Mapping

15.1.1 - CAN1

Address range 00’EF00h 00’EFFFh is reserved

for the CAN1 Module access. The CAN1 is

enabled by setting bit 0 of the new XPERCON

tiplexed addresses and a 16-bit data bus (byte

accesses are possible). Two waitstates give an

access time of 100 ns at 40MHz CPU clock. No

tristate waitstate is used.

15.1.2 - CAN2

Address range 00’EE00h 00’EEFFh is reserved

for the CAN2 Module access. The CAN2 is

enabled by setting XPEN bit 2 of the SYSCON

Accesses to the CAN Module use demultiplexed

addresses and a 16-bit data bus (byte accesses

are possible). Two waitstates give an access time

of 100 ns at 40MHz CPU clock. No tristate wait-

state is used.

Note: If one or the two CAN modules are used,

Port 4 can not be programmed to output all

8 segment address lines. Thus, only 4

segment address lines can be used,

reducing the external memory space to

5M Bytes (1M Byte per CS line).

15.2 - CAN Bus Configurations

Depending on application, CAN bus configuration

may be one single bus with a single or multiple

interfaces or a multiple bus with a single or

multiple interfaces. The ST10F280 is able to

support these 2 cases.

Single CAN Bus

The

single

CAN

Bus

multiple

interfaces

configuration may be implemented using 2 CAN

transceives as shown in Figure 59.

The ST10F280 also supports single CAN Bus

multiple (dual) interfaces using the open drain

option of the CANx_TxD output as shown in Fig-

ure 60. Thanks to the OR-Wired Connection, only

one transceiver is required. In this case the design

of the application must take in account the wire

length and the noise environment.

Figure 59 : Single CAN Bus Multiple Interfaces -

Multiple Transceivers

Figure 60 : Single CAN Bus Dual Interfaces -

Single Transceiver

CAN1

RxD TxD

CAN2

RxD TxD

CAN

Transceiver

CAN

Transceiver

CAN_H

CAN bus

CAN1

RxD TxD

CAN2

RxD TxD

CAN

Transceiver

CAN_H

CAN bus

* Open drain output

+5V

2.7k

Ω

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