ST10F280 datasheet(122/186 Pages) STMICROELECTRONICS

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ST10F280

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Interrupt Register (EF02h/EE02h)

XReg

Reset Value: - - XXh

Table 28 : INTID values and Corresponding Interrupt Sources

Notes 1) Bit INTPND of the corresponding message object has to

be cleared to give messages with a lower priority the

possibility to update INTID or to reset INTID to 00h (idle

state).

2) A message interrupt code is only displayed, if there is no

other interrupt request with a higher priority.

Bit Timing Configuration

According to the CAN protocol specification, a bit

time is subdivided into four segments:

Sync segment, propagation time segment, phase

buffer segment 1 and phase buffer segment 2.

Each segment is a multiple of the time quantum tq

with tq = ( BRP + 1 ) x2 xtXCLK

The Synchronization Segment (Sync seg) is

always 1 tq long. The Propagation Time Segment

and the Phase Buffer Segment1 (combined to

Tseg1) defines the time before the sample point,

while Phase Buffer Segment2 (Tseg2) defines the

time after the sample point. The length of these

segments is programmable (except Sync-Seg).

Note

For exact definition of these segments

please refer to the CAN Specification.

9876543210

RESERVED

INTID

Bit

Function

INTID

Interrupt Identifier

This number indicates the cause of the interrupt. When no interrupt is pending, the value will be “00”.

INTID

Cause of the Interrupt

Interrupt Idle: There is no interrupt request pending.

Status Change Interrupt: The CAN controller has updated (not necessarily changed) the status in the

Control Register. This can refer to a change of the error status of the CAN controller (EIE is set and BOFF

or EWRN change) or to a CAN transfer incident (SIE must be set), like reception or transmission of a

message (RXOK or TXOK is set) or the occurrence of a CAN bus error (LEC is updated). The CPU may

clear RXOK, TXOK, and LEC, however, writing to the status partition of the Control Register can never

generate or reset an interrupt. To update the INTID value the status partition of the Control Register must

be read.

Message 15 Interrupt: Bit INTPND in the Message Control Register of message object 15 (last message)

has been set.

The last message object has the highest interrupt priority of all message objects. 1)

(2+N)

Message N Interrupt: Bit INTPND in the Message Control Register of message object ‘N’ has been set

(N = 1...14). 1) 2)

Figure 63 : Bit Timing Definition

Seg

TSeg1

TSeg2

1 bit time

1 time quantum

sample point

transmit point

Sync

Seg

Sync

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