ST10F280 datasheet(123/186 Pages) STMICROELECTRONICS

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ST10F280

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Bit Timing Register (EF04h/EE04h)

XReg

ResetValue:UUUUh

Note This register can only be written, if the

configuration change enable bit (CCE) is

set.

Mask Registers

Messages

can

use

standard

extended

identifiers. Incoming frames are masked with their

appropriate global masks. Bit IDE of the incoming

message determines whether the standard 11 bit

mask in Global Mask Short or the 29 bit extended

mask in Global Mask Long is to be used. Bit

holding a “0” mean “don’t care”, so do not

compare the message’s identifier in the respective

bit position.

The last message object (15) has an additional

individually

programmable

acceptance

mask

(Mask

Last

Message)

for

the

complete

arbitration field. This allows classes of messages

to be received in this object by masking some bits

of the identifier.

Note The Mask of Last Message is ANDed with

the Global Mask that corresponds to the

incoming message.

Global Mask Short (EF06h/EE06h)

XReg

Reset Value: UFUUh

Upper Global Mask Long (EF08h/EE08h)

XReg

Reset Value: UUUUh

9876543210

TSEG2

TSEG1

SJW

BRP

RRW

Bit

Function

BRP

Baud Rate Prescaler

For generating the bit time quanta the CPU frequency is divided by 2 x (BRP+1).

SJW

(Re)Synchronization Jump Width

Adjust the bit time by maximum (SJW+1) time quanta for re-synchronization.

TSEG1

Time Segment before sample point

There are (TSEG1+1) time quanta before the sample point. Valid values for TSEG1 are “2...15”.

TSEG2

Time Segment after sample point

There are (TSEG2+1) time quanta after the sample point. Valid values for TSEG2 are “1...7”.

9876543210

ID20...18

11111

ID28...21

RRRRR

Bit

Function

ID28...18

Identifier (11 Bit)

Mask to filter incoming messages with standard identifier.

9876543210

ID20...13

ID28...21

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