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ST10F280 数据表(PDF) 124 Page - STMicroelectronics |
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ST10F280 数据表(HTML) 124 Page - STMicroelectronics |
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124 / 186 page  ST10F280 124/186 Lower Global Mask Long (EF0Ah/EE0Ah) XReg Reset Value: UUUUh Upper Mask of Last Message (EF0Ch/EE0Ch) XReg Reset Value: UUUUh Lower Mask of Last Message (EF0Eh/EE0Eh) XReg Reset Value: UUUUh 15.5 - The Message Object The message object is the primary means of communication between CPU and CAN controller. Each of the 15 message objects uses 15 consecutive bytes (see Figure 64) and starts at an address that is a multiple of 16. Note All message objects must be initialized by the CPU, even those which are not going to be used, before clearing the INIT bit. Each element of the Message Control Register is made of two complementary bits. This special mechanism allows the selective setting or resetting of specific elements (leaving others unchanged) without requiring read-modify-write cycles. None of these elements will be affected by reset. The Table 29 shows how to use and to interpret these 2 bit-fields. 15 14 13 12 11 10 9876543210 ID4...0 0 0 0 ID12...5 RW R R R RW Bit Function ID28...0 Identifier (29 bit) Mask to filter incoming messages with extended identifier. 15 14 13 12 11 10 9876543210 ID20...18 ID17...13 ID28...21 RW RW RW 15 14 13 12 11 10 9876543210 ID4...0 0 0 0 ID12...5 RW R R R RW Bit Function ID28...0 Identifier (29 bit) Mask to filter the last incoming message (Nr. 15) with standard or extended identifier (as configured). Figure 64 : Message Object Address Map Message Control Arbitration Message Config. +0 +2 +4 +6 +8 +10 +12 +14 Object Start Address Data0 Reserved Data1 Data2 Data3 Data4 Data5 Data6 Data7 Table 29 : Functions of Complementary Bit of Message Control Register Value Function on Write Meaning on Read 00 Reserved Reserved 01 Reset element Element is reset 10 Set element Element is set 11 Leave element unchanged Reserved |
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