ST10F280 datasheet(120/186 Pages) STMICROELECTRONICS

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ST10F280

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Control / Status Register (EF00h/EE00h)

XReg

Reset Value: XX01h

Table 27 : CAN Control/Status Register

76543210

BOFF EWRN

RXOK TXOK

LEC

TST

CCE

EIE

SIE

INIT

Bit

Function (Control Bit)

INIT

Initialization

Software initialization of the CAN controller. While init is set, all message transfers are stopped.

Setting init does not change the configuration registers and does not stop transmission or

reception of a message in progress. The INIT bit is also set by hardware, following a busoff

condition; the CPU then needs to reset INIT to start the bus recovery sequence.

Disable software initialization of the CAN controller; on INI completion, the CAN waits for 11

consecutive recessive bit before taking part in bus activities.

Interrupt Enable Does not affect status updates.

Global interrupt enable from CAN module.

Global interrupt disable from CAN module.

SIE

Status Change Interrupt Enable

Enables interrupt generation when a message transfer (reception or transmision is successfully

completed) or CAN bus error is detected and registered in LEC is the status partition.

Disable status change interrupt.

EIE

Error Interrupt Enable

Enables interrupt generation on a change of bit BOFF or EWARN in the status partition.

Disable error interrupt.

CCE

Configuration Change Enable

Allows CPU access to the bit timing register

Disables CPU access to the bit timing register

TST

Test Mode (Bit 7)

Make sure that bit 7 is cleared when writing to the Control Register. Writing a 1 during normal operation

may lead erroneous device behaviour.

LEC

Last Error Code

This field holds a code which indicates the type of the last error occurred on the CAN bus. If a message has

been transferred (reception or transmission) without error, this field will be cleared. Code “7” is unused and

may be written by the CPU to check for updates.

No Error

Stuff Error: More than 5 equal bit in a sequence have occurred in a part of a received message

where this is not allowed.

Form Error: A fixed format part of a received frame has the wrong format.

AckError: The message this CAN controller transmitted was not acknowledged by another node

Bit1Error: During the transmission of a message (with the exception of the arbitration field), the

device wanted to send a recessive level (“1”), but the monitored bus value was dominant

Bit0Error: During the transmission of a message (or acknowledge bit, active error flag, or overload

flag), the device wanted to send a

dominant level (“0”), but the monitored bus value was recessive.

During

busoff recovery this status is set each time a sequence of 11 recessive bit has been

monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence

(indicating the bus is not stuck at

dominant or continuously disturbed).

CRCError: The CRC check sum was incorrect in the message received.

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