ST10F280 datasheet(137/186 Pages) STMICROELECTRONICS

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ST10F280

137/186

Exiting Power Down Mode

When Power Down mode is entered, the CPU and

peripheral clocks are frozen, and the oscillator

and PLL are stopped. Power Down mode can be

exited by either asserting RSTIN or one of the

enabled EXxIN pin (Fast External Interrupt).

RSTIN must be held low until the oscillator and

PLL have stabilized.

EXxIN inputs are normally sampled interrupt

inputs. However, the Power Down mode circuitry

uses them as level-sensitive inputs. An EXxIN (x =

7...0) Interrupt Enable bit (bit CCxIE in respective

CCxIC register) need not to be set to bring the

device out of Power Down mode. An external RC

circuit must be connected, as shown in the follow-

ing figure:

To exit Power Down mode with external interrupt,

an EXxIN pin has to be asserted for at least 40 ns

(x = 7...0). This signal enables the internal oscilla-

tor and PLL circuitry, and also turns on the weak

pull-down (see following figure). The discharging

of the external capacitor provides a delay that

allows the oscillator and PLL circuits to stabilize

before the internal CPU and Peripheral clocks are

enabled. When the Vpp voltage drops below the

threshold voltage (about 2.5 V), the Schmitt trig-

ger clears Q2 flip-flop, thus enabling the CPU and

Peripheral clocks, and the device resumes code

execution.

If the Interrupt was enabled (bit CCxIE=’1’ in the

respective CCxIC register) before entering Power

Down mode, the device executes the interrupt ser-

vice routine, and then resumes execution after the

PWRDN intruction (see note below). If the inter-

rupt was disabled, the device executes the

instruction following PWRDN instruction, and the

Interrupt Request Flag (bit CCxIR in the respec-

tive CCxIC register) remains set until it is cleared

by software.

Note: Due to internal pipeline, the instruction that

follows the PWRDN intruction is executed

before the CPU performs a call of the

interrupt service routine when exiting

power-down mode.

Figure 71 : External RC Circuit on RPD Pin for Exiting

Powerdown Mode with External Interrup

RPD

VDD

220k

Ω 1MΩ Typical

µF Typical

ST10F280

Figure 72 : Simplified Powerdown Exit Circuitry

VDD

Enter

External

interrupt

reset

Stop pll

stop oscillator

VDD

System clock

CPU and Peripherals clocks

RPD

VDD

Pull-up

Weak Pull-down

(~ 200

µA)

PowerDown

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