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ST10F280 数据表(PDF) 134 Page - STMicroelectronics

部件名 ST10F280
功能描述  16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM
PDF  186 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST10F280 数据表(HTML) 134 Page - STMicroelectronics

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ST10F280
Table 33 : PORT0 Latched Configuration for the Different Resets
Notes: 1. Not latched from PORT0.
2. Only RP0H low byte is used and the bit-fields are latched from PORT0 high byte to RP0H low byte.
3. Indirectly depend on PORT0.
4. Bits set if EA pin is 1.
Figure 70 : External Reset Hardware Circuitry
X : Pin is sampled
- : Pin is not sampled
PORT0
Sample event
Software Reset
-
-
-
XXXXXXX
-----
-
Watchdog Reset
-
-
-
XXXXXXX
-----
-
Short Hardware Reset
-
-
-
XXXXXXXXX
XXXX
Long Hardware Reset
XXXXXXXXXXXX
XXXX
Power-On Reset
XXXXXXXXXXXX
XXXX
Table 34 : PORT0 bit latched into the different registers after reset
PORT0 bit
nber
h7
h6
h5
h4
h3
h2
h1
h0
I7
I6
I5
I4
I3
I2
I1
I0
PORT0 bit
Name
CLKCFG
CLKCFG
CLKCFG
SALSEL
SALSEL
CSSEL
CSSEL
WRC
BUSTYP
BUSTYP
R
BSL
R
R
ADP
EMU
RP0H
2
X
1
X
1
X
1
X
1
X
1
X
1
X
1
X
1
CLKCFG
CLKCFG
CLKCFG SALSEL SALSEL
CSSEL CSSEL
WRC
SYSCON
X 1
X 1
X 1
X 1
X 1
X 1
BYTDIS 3
X 1
WRCFG 3
X 1
X 1
X 1
X 1
X 1
X 1
X 1
BUSCON0
X 1
X 1
X 1
X 1
-BUS
ACT0 4
ALE
CTL0 4
-
BTYP
BTYP
X 1
X 1
X 1
X 1
X 1
X 1
Internal Logic
To Clock Generator
To Port 4 Logic
To Port 6 Logic
X
1
X
1
X
1
X
1
Internal
X
1
X
1
Internal Internal
ST10F280
External
Hardware
RSTOUT
+
RSTIN
VDD
C1
D2
R1
D1
VDD
R2
Open Drain Inverter
External
Reset Source
VDD
R0
RPD
+
C0



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