ST10F280 datasheet(131/186 Pages) STMICROELECTRONICS

131 / 186 page

ST10F280

131/186

Figure 67 : Synchronous Warm Reset (Long low pulse on RSTIN)

Notes: 1. RSTIN rising edge to internal latch of PORT0 is 3 CPU

(6 TCL) clock cycles if the PLL is bypassed and the

prescaler is on (fCPU = fXTAL / 2), else it is 4 CPU clock

cycles (8 TCL).

2. If during the reset condition (RSTIN low), VRPD voltage

drops below the threshold voltage (about 2.5V for 5V

operation), the asynchronous reset is then immediately

entered.

3. RSTIN pin is pulled low if bit BDRSTEN (bit 5 of

SYSCON register) was previously set by soft-ware. Bit

BDRSTEN is cleared after reset.

17.3 - Software Reset

The reset sequence can be triggered at any time

using the protected instruction SRST (software

reset).

This

instruction

can

executed

deliberately within a program, for example to leave

bootstrap loader mode, or upon a hardware trap

that reveals a system failure.

Upon execution of the SRST instruction, the

internal reset sequence (1024 TCL) is started.

The microcontroller behaviour is the same as for a

Short

Hardware

reset,

except

that

only

P0.12...P0.6 bit are latched at the end of the reset

sequence, while P0.5...P0.2 bit are cleared.

17.4 - Watchdog Timer Reset

When the watchdog timer is not disabled during

the initialization or when it is not regularly serviced

during program execution it will overflow and it will

trigger the reset sequence.

Unlike

hardware

and

software

resets,

the

watchdog reset completes a running external bus

cycle if this bus cycle either does not use READY,

or if READY is sampled active (low) after the

programmed

wait

states.

When

READY

sampled inactive (high) after the programmed wait

states the running external bus cycle is aborted.

Then the internal reset sequence is started. At the

end of the internal reset sequence (1024 TCL),

only P0.12...P0.6 bit are latched, while previously

latched values of P0.5...P0.2 are cleared.

17.5 - RSTOUT Pin and Bidirectional Reset

The RSTOUT pin is driven active (low level) at the

beginning of any reset sequence (synchronous/

asynchronous hardware, software and watchdog

timer resets). RSTOUT pin stays active low

beyond the end of the initialization routine, until

the

protected

EINIT

instruction

(End

Initialization) is completed.

The Bidirectional Reset function is useful when

external devices require a reset signal but cannot

be connected to RSTOUT pin, because RSTOUT

signal lasts during initialisation. It is, for instance,

the case of external memory running initialization

routine before the execution of EINIT instruction.

Bidirectional reset function is enabled by setting

bit 3 (BDRSTEN) in SYSCON register. It only can

be enabled during the initialization routine, before

EINIT instruction is completed.

CPU Clock

RSTIN

RPD

RSTOUT

ALE

PORT0

Internal

Reset

Signal

Latching point of PORT0

for system start-up configuration

6 or 8 TCL1

4 TCL

12 TCL

1024 TCL

Internally pulled low3

Reset Configuration

2 V

RPD > 2.5V Asynchronous Reset not entered.

200

µA Discharge

ST10F280 数据表(PDF) 131 Page - STMicroelectronics

ST10F280 数据表(HTML) 131 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载